Class information for:
Level 1: FLIP FLOP//PULSED LATCH//LEVEL CONVERTER

Basic class information
Class id #P Avg. number of
references		 Database coverage
of references
22822 367 13.6 48%


Bar chart of Publication_year

Last years might be incomplete

Hierarchy of classes
The table includes all classes above and classes immediately below the current class.


Cluster id Level Cluster label #P
9 4 COMPUTER SCIENCE, THEORY & METHODS//COMPUTER SCIENCE, ARTIFICIAL INTELLIGENCE//COMPUTER SCIENCE, INFORMATION SYSTEMS 1247339
264 3       COMPUTER SCIENCE, HARDWARE & ARCHITECTURE//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//ENGINEERING, ELECTRICAL & ELECTRONIC 44494
470 2             COMPUTER SCIENCE, HARDWARE & ARCHITECTURE//IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS//NETWORK ON CHIP 15913
22822 1                   FLIP FLOP//PULSED LATCH//LEVEL CONVERTER 367

Terms with highest relevance score


rank Term termType Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 FLIP FLOP authKW 871995 17% 17% 61
2 PULSED LATCH authKW 481376 2% 64% 9
3 LEVEL CONVERTER authKW 437895 3% 53% 10
4 CLOCK GATING authKW 400731 5% 28% 17
5 PULSE TRIGGERED authKW 346673 1% 83% 5
6 CLOCKING authKW 251670 3% 28% 11
7 CONDITIONAL PRECHARGE authKW 249606 1% 100% 3
8 DOUBLE EDGE TRIGGERED authKW 249606 1% 100% 3
9 INTEGRATED CIRCUIT DESIGN EMBEDDED SYST address 249606 1% 100% 3
10 PULSE TRIGGERED FLIP FLOP authKW 249606 1% 100% 3

Web of Science journal categories


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 Computer Science, Hardware & Architecture 11372 31% 0% 115
2 Engineering, Electrical & Electronic 8948 89% 0% 326
3 Computer Science, Information Systems 319 8% 0% 30
4 Computer Science, Theory & Methods 112 5% 0% 20
5 Computer Science, Interdisciplinary Applications 105 5% 0% 19
6 Computer Science, Software Engineering 53 3% 0% 12
7 Nanoscience & Nanotechnology 9 3% 0% 10
8 Instruments & Instrumentation 4 2% 0% 7
9 Telecommunications 3 1% 0% 5
10 Materials Science, Textiles 1 0% 0% 1

Address terms


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 INTEGRATED CIRCUIT DESIGN EMBEDDED SYST 249606 1% 100% 3
2 GLOBAL INFORMAT TECHNOL 110935 1% 67% 2
3 NICS GRP 110935 1% 67% 2
4 ADV INTEGRATED SYST 83202 0% 100% 1
5 BROADBAND LSI PROJECT 83202 0% 100% 1
6 CL AIP ADV MACROS ARCHITECTU 83202 0% 100% 1
7 DISENO DIGITAL MIXTO 83202 0% 100% 1
8 DPT DIESIA 83202 0% 100% 1
9 ENGR SCI TECHNOL 83202 0% 100% 1
10 LOG ANALOG IP DEV 83202 0% 100% 1

Journals


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 49744 12% 1% 45
2 IEEE JOURNAL OF SOLID-STATE CIRCUITS 30551 15% 1% 55
3 JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 8046 4% 1% 13
4 IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 5836 2% 1% 8
5 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 4690 4% 0% 15
6 VLSI DESIGN 4664 1% 1% 5
7 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 4504 5% 0% 17
8 ELECTRONICS LETTERS 3905 12% 0% 43
9 IEEE CIRCUITS & DEVICES 3851 1% 1% 4
10 IEICE TRANSACTIONS ON ELECTRONICS 3535 4% 0% 16

Author Key Words


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class		 LCSH search Wikipedia search
1 FLIP FLOP 871995 17% 17% 61 Search FLIP+FLOP Search FLIP+FLOP
2 PULSED LATCH 481376 2% 64% 9 Search PULSED+LATCH Search PULSED+LATCH
3 LEVEL CONVERTER 437895 3% 53% 10 Search LEVEL+CONVERTER Search LEVEL+CONVERTER
4 CLOCK GATING 400731 5% 28% 17 Search CLOCK+GATING Search CLOCK+GATING
5 PULSE TRIGGERED 346673 1% 83% 5 Search PULSE+TRIGGERED Search PULSE+TRIGGERED
6 CLOCKING 251670 3% 28% 11 Search CLOCKING Search CLOCKING
7 CONDITIONAL PRECHARGE 249606 1% 100% 3 Search CONDITIONAL+PRECHARGE Search CONDITIONAL+PRECHARGE
8 DOUBLE EDGE TRIGGERED 249606 1% 100% 3 Search DOUBLE+EDGE+TRIGGERED Search DOUBLE+EDGE+TRIGGERED
9 PULSE TRIGGERED FLIP FLOP 249606 1% 100% 3 Search PULSE+TRIGGERED+FLIP+FLOP Search PULSE+TRIGGERED+FLIP+FLOP
10 FLIP FLOPS FFS 190172 1% 57% 4 Search FLIP+FLOPS+FFS Search FLIP+FLOPS+FFS

Core articles
The table includes core articles in the class. The following variables is taken into account for the relevance score of an article in a cluster c:
(1) Number of references referring to publications in the class.
(2) Share of total number of active references referring to publications in the class.
(3) Age of the article. New articles get higher score than old articles.
(4) Citation rate, normalized to year.


Rank Reference # ref.
in cl.		 Shr. of ref. in
cl.		 Citations
1 SINGH, K , TIWARI, SC , GUPTA, M , (2014) A MODIFIED IMPLEMENTATION OF TRISTATE INVERTER BASED STATIC MASTER-SLAVE FLIP-FLOP WITH IMPROVED POWER-DELAY-AREA PRODUCT.SCIENTIFIC WORLD JOURNAL. VOL. . ISSUE . P. - 18 90% 0
2 GENG, L , SHEN, JZ , XU, CY , (2016) POWER-EFFICIENT DUAL-EDGE IMPLICIT PULSE-TRIGGERED FLIP-FLOP WITH AN EMBEDDED CLOCK-GATING SCHEME.FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING. VOL. 17. ISSUE 9. P. 962 -972 16 94% 0
3 RAHIMINEJAD, M , SANEEI, M , (2014) LOW-POWER PULSED HYBRID FLIP-FLOP BASED ON A C-ELEMENT.AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS. VOL. 68. ISSUE 9. P. 907 -913 16 94% 0
4 LIN, JF , (2014) LOW-POWER PULSE-TRIGGERED FLIP-FLOP DESIGN BASED ON A SIGNAL FEED-THROUGH SCHEME.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. VOL. 22. ISSUE 1. P. 181-185 15 94% 4
5 GENG, L , SHEN, JZ , XU, CY , (2016) DESIGN OF FLIP-FLOPS WITH CLOCK-GATING AND PULL-UP CONTROL SCHEME FOR POWER-CONSTRAINED AND SPEED-INSENSITIVE APPLICATIONS.IET COMPUTERS AND DIGITAL TECHNIQUES. VOL. 10. ISSUE 4. P. 193 -201 13 87% 0
6 ALIOTO, M , CONSOLI, E , PALUMBO, G , (2015) VARIATIONS IN NANOMETER CMOS FLIP-FLOPS: PART I-IMPACT OF PROCESS VARIATIONS ON TIMING.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS. VOL. 62. ISSUE 8. P. 2035 -2043 15 71% 3
7 HWANG, YT , LIN, JF , SHEU, MH , (2012) LOW-POWER PULSE-TRIGGERED FLIP-FLOP DESIGN WITH CONDITIONAL PULSE-ENHANCEMENT SCHEME.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. VOL. 20. ISSUE 2. P. 361 -366 11 100% 19
8 LI, XY , JIA, S , LIU, LM , WANG, Y , ZHANG, GG , (2012) DESIGN OF NOVEL, SEMI-TRANSPARENT FLIP-FLOPS (STFF) FOR HIGH SPEED AND LOW POWER APPLICATION.SCIENCE CHINA-INFORMATION SCIENCES. VOL. 55. ISSUE 10. P. 2390 -2398 11 100% 1
9 ALIOTO, M , CONSOLI, E , PALUMBO, G , (2011) ANALYSIS AND COMPARISON IN THE ENERGY-DELAY-AREA DOMAIN OF NANOMETER CMOS FLIP-FLOPS: PART I-METHODOLOGY AND DESIGN STRATEGIES.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. VOL. 19. ISSUE 5. P. 725 -736 14 74% 19
10 ABSEL, K , MANUEL, L , KAVITHA, RK , (2013) LOW-POWER DUAL DYNAMIC NODE PULSED HYBRID FLIP-FLOP FEATURING EFFICIENT EMBEDDED LOGIC.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. VOL. 21. ISSUE 9. P. 1693 -1704 9 100% 8

Classes with closest relation at Level 1


Rank Class id link
1 30713 ADIABATIC CIRCUIT//ADIABATIC LOGIC//ADIABATIC CHARGING
2 15984 POWER ESTIMATION//SWITCHING ACTIVITY//BUS ENCODING
3 3550 SRAM//PROCESS VARIATION//POWER GATING
4 5076 BUFFER INSERTION//CLOCK SKEW//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
5 8568 MULTIPLE VALUED LOGIC//FULL ADDER//FIXED WIDTH MULTIPLIER
6 13551 ASYNCHRONOUS CIRCUITS//SIGNAL TRANSITION GRAPHS//ASYNCHRONOUS DESIGN
7 30433 RETIMING//CLOCK SCHEDULING//SEMI SYNCHRONOUS CIRCUIT
8 30618 CRC 32//CYCLIC REDUNDANCY CHECKS//DIGITAL BROADCASTING SYSTEM
9 18911 SELF CHECKING CIRCUITS//ITERATIVE LOGIC ARRAYS//CONCURRENT ERROR DETECTION
10 30345 HORIZONTAL CURRENT BIPOLAR TRANSISTOR HCBT//LATERAL BIPOLAR TRANSISTOR//ABT BAUELEMENTETECHNOL

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