Class information for:
Level 1: RETIMING//CLOCK SCHEDULING//SEMI SYNCHRONOUS CIRCUIT

Basic class information

Class id #P Avg. number of
references
Database coverage
of references
30433 169 21.4 33%



Bar chart of Publication_year

Last years might be incomplete

Hierarchy of classes

The table includes all classes above and classes immediately below the current class.



Cluster id Level Cluster label #P
9 4 COMPUTER SCIENCE, THEORY & METHODS//COMPUTER SCIENCE, ARTIFICIAL INTELLIGENCE//COMPUTER SCIENCE, INFORMATION SYSTEMS 1247339
264 3       COMPUTER SCIENCE, HARDWARE & ARCHITECTURE//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//ENGINEERING, ELECTRICAL & ELECTRONIC 44494
470 2             COMPUTER SCIENCE, HARDWARE & ARCHITECTURE//IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS//NETWORK ON CHIP 15913
30433 1                   RETIMING//CLOCK SCHEDULING//SEMI SYNCHRONOUS CIRCUIT 169

Terms with highest relevance score



rank Term termType Chi square Shr. of publ. in
class containing
term
Class's shr. of
term's tot. occurrences
#P with
term in
class
1 RETIMING authKW 1767514 18% 33% 30
2 CLOCK SCHEDULING authKW 1290590 6% 71% 10
3 SEMI SYNCHRONOUS CIRCUIT authKW 1264784 4% 100% 7
4 GENERAL SYNCHRONOUS FRAMEWORK authKW 903417 3% 100% 5
5 CLOCK PERIOD MINIMIZATION authKW 722733 2% 100% 4
6 COMP SCI SOFTWARE ENGR address 406536 2% 75% 3
7 CLOCK SCHEDULE authKW 361367 1% 100% 2
8 DIGITAL FILTER OPTIMIZATION authKW 361367 1% 100% 2
9 LEVEL SENSITIVE LATCH authKW 361367 1% 100% 2
10 MULTI CLOCK CYCLE PATHS authKW 361367 1% 100% 2

Web of Science journal categories



Rank Term Chi square Shr. of publ. in
class containing
term
Class's shr. of
term's tot. occurrences
#P with
term in
class
1 Computer Science, Hardware & Architecture 22830 65% 0% 110
2 Engineering, Electrical & Electronic 2074 64% 0% 108
3 Computer Science, Information Systems 1595 25% 0% 43
4 Computer Science, Software Engineering 1103 19% 0% 32
5 Computer Science, Interdisciplinary Applications 967 21% 0% 35
6 Computer Science, Theory & Methods 625 17% 0% 29
7 COMPUTER APPLICATIONS & CYBERNETICS 273 1% 0% 2
8 Telecommunications 30 4% 0% 7
9 Computer Science, Artificial Intelligence 1 1% 0% 2
10 Nanoscience & Nanotechnology 0 1% 0% 2

Address terms



Rank Term Chi square Shr. of publ. in
class containing
term
Class's shr. of
term's tot. occurrences
#P with
term in
class
1 COMP SCI SOFTWARE ENGR 406536 2% 75% 3
2 ELEC COMP ENGR 271022 2% 50% 3
3 ENGR COMP 180683 1% 100% 1
4 LS PROF PAUL 180683 1% 100% 1
5 MOS DESIGN 180683 1% 100% 1
6 LOG SYNTH GRP 90341 1% 50% 1
7 COMMUN INTEGRATED SYST 70560 6% 4% 10
8 ENTERPRISE SYST GRP 60224 1% 17% 2
9 COMP SCI ENGR 45169 1% 25% 1
10 COMP SCI SOFTWARE 28523 2% 5% 3

Journals



Rank Term Chi square Shr. of publ. in
class containing
term
Class's shr. of
term's tot. occurrences
#P with
term in
class
1 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 43079 20% 1% 34
2 JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 42899 9% 2% 15
3 ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 19367 5% 1% 9
4 INTEGRATION-THE VLSI JOURNAL 14810 5% 1% 9
5 JOURNAL OF VLSI AND COMPUTER SYSTEMS 11291 1% 6% 1
6 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 10023 12% 0% 21
7 JOURNAL OF SYSTEMS ARCHITECTURE 5225 4% 0% 6
8 JOURNAL OF DIGITAL SYSTEMS 4753 1% 3% 1
9 VLSI DESIGN 3648 2% 1% 3
10 FORMAL METHODS IN SYSTEM DESIGN 3233 2% 1% 3

Author Key Words



Rank Term Chi square Shr. of publ. in
class containing
term
Class's shr. of
term's tot. occurrences
#P with
term in
class
LCSH search Wikipedia search
1 RETIMING 1767514 18% 33% 30 Search RETIMING Search RETIMING
2 CLOCK SCHEDULING 1290590 6% 71% 10 Search CLOCK+SCHEDULING Search CLOCK+SCHEDULING
3 SEMI SYNCHRONOUS CIRCUIT 1264784 4% 100% 7 Search SEMI+SYNCHRONOUS+CIRCUIT Search SEMI+SYNCHRONOUS+CIRCUIT
4 GENERAL SYNCHRONOUS FRAMEWORK 903417 3% 100% 5 Search GENERAL+SYNCHRONOUS+FRAMEWORK Search GENERAL+SYNCHRONOUS+FRAMEWORK
5 CLOCK PERIOD MINIMIZATION 722733 2% 100% 4 Search CLOCK+PERIOD+MINIMIZATION Search CLOCK+PERIOD+MINIMIZATION
6 CLOCK SCHEDULE 361367 1% 100% 2 Search CLOCK+SCHEDULE Search CLOCK+SCHEDULE
7 DIGITAL FILTER OPTIMIZATION 361367 1% 100% 2 Search DIGITAL+FILTER+OPTIMIZATION Search DIGITAL+FILTER+OPTIMIZATION
8 LEVEL SENSITIVE LATCH 361367 1% 100% 2 Search LEVEL+SENSITIVE+LATCH Search LEVEL+SENSITIVE+LATCH
9 MULTI CLOCK CYCLE PATHS 361367 1% 100% 2 Search MULTI+CLOCK+CYCLE+PATHS Search MULTI+CLOCK+CYCLE+PATHS
10 REGISTER RELOCATION 361367 1% 100% 2 Search REGISTER+RELOCATION Search REGISTER+RELOCATION

Core articles

The table includes core articles in the class. The following variables is taken into account for the relevance score of an article in a cluster c:
(1) Number of references referring to publications in the class.
(2) Share of total number of active references referring to publications in the class.
(3) Age of the article. New articles get higher score than old articles.
(4) Citation rate, normalized to year.



Rank Reference # ref.
in cl.
Shr. of ref. in
cl.
Citations
1 KAWAGUCHI, J , MASHIKO, H , KOHIRA, Y , (2016) TECHNOLOGY MAPPING METHOD USING INTEGER LINEAR PROGRAMMING FOR LOW POWER CONSUMPTION AND HIGH PERFORMANCE IN GENERAL-SYNCHRONOUS FRAMEWORK.IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES. VOL. E99A. ISSUE 7. P. - 8 100% 0
2 KOHIRA, Y , TAKAHASHI, A , (2008) A FAST GATE-LEVEL REGISTER RELOCATION METHOD FOR CIRCUIT SIZE REDUCTION IN GENERAL-SYNCHRONOUS FRAMEWORK.IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES. VOL. E91A. ISSUE 10. P. 3030 -3037 9 100% 0
3 ZHOU, H , (2008) A NEW EFFICIENT RETIMING ALGORITHM DERIVED BY FORMAL MANIPULATION.ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS. VOL. 13. ISSUE 1. P. - 9 90% 1
4 KOHIRA, Y , TAKAHASHI, A , (2007) GATE-LEVEL REGISTER RELOCATION IN GENERALIZED SYNCHRONOUS FRAMEWORK FOR CLOCK PERIOD MINIMIZATION.IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES. VOL. E90A. ISSUE 4. P. 800 -807 7 100% 0
5 JIANG, JHR , BRAYTON, RK , (2006) RETIMING AND RESYNTHESIS: A COMPLEXITY PERSPECTIVE.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. VOL. 25. ISSUE 12. P. 2674 -2686 8 73% 5
6 MAHESHWARI, N , SAPATNEKAR, SS , (1999) RETIMING CONTROL LOGIC.INTEGRATION-THE VLSI JOURNAL. VOL. 28. ISSUE 1. P. 33 -53 8 89% 0
7 NEUMANN, I , KUNZ, W , (2003) LAYOUT DRIVEN RETIMING USING THE COUPLED EDGE TIMING MODEL.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. VOL. 22. ISSUE 7. P. 825 -835 6 100% 2
8 TONG, DKY , YOUNG, EFY , CHU, C , DECHU, S , (2007) WIRE RETIMING PROBLEM WITH NET TOPOLOGY OPTIMIZATION.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. VOL. 26. ISSUE 9. P. 1648 -1660 6 86% 2
9 JIANG, JHR , (2005) ON SOME TRANSFORMATION INVARIANTS UNDER RETIMING AND RESYNTHESIS.TOOLS AND ALGORITHMS FOR THE CONSTRUCTION AND ANALYSIS OF SYSTEMS, PROCEEDINGS. VOL. 3440. ISSUE . P. 413-428 7 78% 0
10 ABOULHAMID, EM , CHABINI, N , CHABINI, I , SAVARIA, Y , (2005) SCHEDULING AND OPTIMAL REGISTER PLACEMENT FOR SYNCHRONOUS CIRCUITS DERIVED USING SOFTWARE PIPELINING TECHNIQUES.ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS. VOL. 10. ISSUE 2. P. 187 -204 7 70% 0

Classes with closest relation at Level 1



Rank Class id link
1 13875 HIGH LEVEL SYNTHESIS//BEHAVIORAL SYNTHESIS//DATAPATH SYNTHESIS
2 12738 SYNCHRONOUS DATAFLOW//DESIGN SPACE EXPLORATION//DATAFLOW GRAPHS
3 5076 BUFFER INSERTION//CLOCK SKEW//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
4 11675 ALGORITHM BASED FAULT TOLERANCE//SYSTOLIC ARRAY//ALGORITHM TRANSFORMATION
5 22822 FLIP FLOP//PULSED LATCH//LEVEL CONVERTER
6 17996 STATE ASSIGNMENT//LOGIC SYNTHESIS//LOGIC OPTIMIZATION
7 14808 ORDERED BINARY DECISION DIAGRAMS//BINARY DECISION DIAGRAMS//BRANCHING PROGRAMS
8 13551 ASYNCHRONOUS CIRCUITS//SIGNAL TRANSITION GRAPHS//ASYNCHRONOUS DESIGN
9 10145 REGISTER ALLOCATION//INSTRUCTION SCHEDULING//INSTRUCTION LEVEL PARALLELISM
10 4952 PARALLELIZING COMPILERS//LOOP TRANSFORMATIONS//AUTOMATIC PARALLELIZATION

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