Class information for:
Level 1: HIGH LEVEL SYNTHESIS//BEHAVIORAL SYNTHESIS//DATAPATH SYNTHESIS

Basic class information
Class id #P Avg. number of
references		 Database coverage
of references
13875 807 22.9 25%


Bar chart of Publication_year

Last years might be incomplete

Hierarchy of classes
The table includes all classes above and classes immediately below the current class.


Cluster id Level Cluster label #P
9 4 COMPUTER SCIENCE, THEORY & METHODS//COMPUTER SCIENCE, ARTIFICIAL INTELLIGENCE//COMPUTER SCIENCE, INFORMATION SYSTEMS 1247339
264 3       COMPUTER SCIENCE, HARDWARE & ARCHITECTURE//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//ENGINEERING, ELECTRICAL & ELECTRONIC 44494
470 2             COMPUTER SCIENCE, HARDWARE & ARCHITECTURE//IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS//NETWORK ON CHIP 15913
13875 1                   HIGH LEVEL SYNTHESIS//BEHAVIORAL SYNTHESIS//DATAPATH SYNTHESIS 807

Terms with highest relevance score


rank Term termType Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 HIGH LEVEL SYNTHESIS authKW 2421722 20% 40% 162
2 BEHAVIORAL SYNTHESIS authKW 472934 3% 50% 25
3 DATAPATH SYNTHESIS authKW 333992 2% 55% 16
4 RESOURCE BINDING authKW 242152 1% 80% 8
5 MODULE SELECTION authKW 235746 1% 69% 9
6 DATA PATH ALLOCATION authKW 227020 1% 100% 6
7 HIGH LEVEL SYNTHESIS HLS authKW 211869 2% 40% 14
8 MULTIPLE VOLTAGES authKW 189183 1% 100% 5
9 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS journal 157324 18% 3% 142
10 INTERCONNECTION DELAY authKW 154494 1% 58% 7

Web of Science journal categories


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 Computer Science, Hardware & Architecture 99528 62% 1% 502
2 Engineering, Electrical & Electronic 9998 64% 0% 518
3 Computer Science, Interdisciplinary Applications 4004 19% 0% 156
4 Computer Science, Software Engineering 2772 14% 0% 112
5 Computer Science, Theory & Methods 1911 14% 0% 112
6 Computer Science, Information Systems 1672 12% 0% 99
7 Computer Science, Artificial Intelligence 46 3% 0% 21
8 COMPUTER APPLICATIONS & CYBERNETICS 13 0% 0% 1
9 Nanoscience & Nanotechnology 8 2% 0% 17
10 Computer Science, Cybernetics 8 0% 0% 3

Address terms


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 CIRCUIT DESIGN FAULT TOLERANCE 75673 0% 100% 2
2 ADV DIGITAL SCI ILLINOIS 37837 0% 100% 1
3 BEHAV COMPILER GRP 37837 0% 100% 1
4 CNRS E RECH 37837 0% 100% 1
5 DESIGN TECHNOL ENABLEMENT GRP 37837 0% 100% 1
6 DESIGN TECHNOL RD 37837 0% 100% 1
7 DIGIATAL SIGNAL PROC 37837 0% 100% 1
8 DSIP GRP 37837 0% 100% 1
9 ELECT ENGN VLSI DESIGN 37837 0% 100% 1
10 EMBEDDED COMP SYSTEMS 37837 0% 100% 1

Journals


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 157324 18% 3% 142
2 MICROPROCESSING AND MICROPROGRAMMING 71396 6% 4% 46
3 IEEE DESIGN & TEST OF COMPUTERS 41768 4% 3% 33
4 INTEGRATION-THE VLSI JOURNAL 39193 4% 3% 32
5 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 31331 7% 2% 53
6 JOURNAL OF VLSI SIGNAL PROCESSING 30251 1% 8% 10
7 ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 26466 3% 3% 23
8 IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 16024 2% 2% 17
9 IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 10916 6% 1% 48
10 IFIP TRANSACTIONS A-COMPUTER SCIENCE AND TECHNOLOGY 8747 2% 2% 15

Author Key Words


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class		 LCSH search Wikipedia search
1 HIGH LEVEL SYNTHESIS 2421722 20% 40% 162 Search HIGH+LEVEL+SYNTHESIS Search HIGH+LEVEL+SYNTHESIS
2 BEHAVIORAL SYNTHESIS 472934 3% 50% 25 Search BEHAVIORAL+SYNTHESIS Search BEHAVIORAL+SYNTHESIS
3 DATAPATH SYNTHESIS 333992 2% 55% 16 Search DATAPATH+SYNTHESIS Search DATAPATH+SYNTHESIS
4 RESOURCE BINDING 242152 1% 80% 8 Search RESOURCE+BINDING Search RESOURCE+BINDING
5 MODULE SELECTION 235746 1% 69% 9 Search MODULE+SELECTION Search MODULE+SELECTION
6 DATA PATH ALLOCATION 227020 1% 100% 6 Search DATA+PATH+ALLOCATION Search DATA+PATH+ALLOCATION
7 HIGH LEVEL SYNTHESIS HLS 211869 2% 40% 14 Search HIGH+LEVEL+SYNTHESIS+HLS Search HIGH+LEVEL+SYNTHESIS+HLS
8 MULTIPLE VOLTAGES 189183 1% 100% 5 Search MULTIPLE+VOLTAGES Search MULTIPLE+VOLTAGES
9 INTERCONNECTION DELAY 154494 1% 58% 7 Search INTERCONNECTION+DELAY Search INTERCONNECTION+DELAY
10 CONTROL FLOW INTENSIVE BEHAVIORS 113510 0% 100% 3 Search CONTROL+FLOW+INTENSIVE+BEHAVIORS Search CONTROL+FLOW+INTENSIVE+BEHAVIORS

Core articles
The table includes core articles in the class. The following variables is taken into account for the relevance score of an article in a cluster c:
(1) Number of references referring to publications in the class.
(2) Share of total number of active references referring to publications in the class.
(3) Age of the article. New articles get higher score than old articles.
(4) Citation rate, normalized to year.


Rank Reference # ref.
in cl.		 Shr. of ref. in
cl.		 Citations
1 AHMAD, I , DHODHI, MK , ALI, FM , (2000) TLS: A TABU SEARCH BASED SCHEDULING ALGORITHM FOR BEHAVIORAL SYNTHESIS OF FUNCTIONAL PIPELINES.COMPUTER JOURNAL. VOL. 43. ISSUE 2. P. 152-166 21 84% 4
2 SHEN, ZX , JONG, QC , (2002) LOWER BOUND ESTIMATION OF HARDWARE RESOURCES FOR SCHEDULING IN HIGH-LEVEL SYNTHESIS.JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY. VOL. 17. ISSUE 6. P. 718 -730 15 100% 2
3 WU, YH , YU, CJ , WANG, SD , (2009) HEURISTIC ALGORITHM FOR THE RESOURCE-CONSTRAINED SCHEDULING PROBLEM DURING HIGH-LEVEL SYNTHESIS.IET COMPUTERS AND DIGITAL TECHNIQUES. VOL. 3. ISSUE 1. P. 43 -51 12 100% 4
4 CHENG, HD , XIA, C , (1995) HIGH-LEVEL SYNTHESIS - CURRENT STATUS AND FUTURE-PROSPECTS.CIRCUITS SYSTEMS AND SIGNAL PROCESSING. VOL. 14. ISSUE 3. P. 351-400 19 95% 0
5 TOGAWA, N , HISAKI, T , YANAGISAWA, M , OHTSUKI, T , (1998) A HIGH-LEVEL SYNTHESIS SYSTEM FOR DIGITAL SIGNAL PROCESSING BASED ON DATA-FLOW GRAPH ENUMERATION.IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES. VOL. E81A. ISSUE 12. P. 2563 -2575 17 85% 0
6 ABE, S , SHI, YH , USAMI, K , YANAGISAWA, M , TOGAWA, N , (2013) FLOORPLAN DRIVEN ARCHITECTURE AND HIGH-LEVEL SYNTHESIS ALGORITHM FOR DYNAMIC MULTIPLE SUPPLY VOLTAGES.IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES. VOL. E96A. ISSUE 12. P. 2597 -2611 9 100% 0
7 ISMAEEL, AA , BHATNAGAR, R , MATHEW, R , (2002) ON-LINE TESTABLE DATA PATH SYNTHESIS FOR MINIMIZING TESTING TIME.MICROELECTRONICS RELIABILITY. VOL. 42. ISSUE 3. P. 437 -453 12 100% 0
8 CHANG, YN , WANG, CY , PARHI, KK , (1998) HEURISTIC LOOP-BASED SCHEDULING AND ALLOCATION FOR DSP SYNTHESIS WITH HETEROGENEOUS FUNCTIONAL UNITS.JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY. VOL. 19. ISSUE 3. P. 243 -256 16 84% 5
9 KRISHNAN, V , KATKOORI, S , (2006) A GENETIC ALGORITHM FOR THE DESIGN SPACE EXPLORATION OF DATAPATHS DURING HIGH-LEVEL SYNTHESIS.IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION. VOL. 10. ISSUE 3. P. 213-229 13 76% 28
10 ITO, K , LUCKE, LE , PARHI, KK , (1998) ILP-BASED COST-OPTIMAL DSP SYNTHESIS WITH MODULE SELECTION AND DATA FORMAT CONVERSION.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. VOL. 6. ISSUE 4. P. 582-594 18 69% 21

Classes with closest relation at Level 1


Rank Class id link
1 30433 RETIMING//CLOCK SCHEDULING//SEMI SYNCHRONOUS CIRCUIT
2 21132 HARDWARE SOFTWARE PARTITIONING//HARDWARE SOFTWARE COSYNTHESIS//HARDWARE SOFTWARE CODESIGN
3 15984 POWER ESTIMATION//SWITCHING ACTIVITY//BUS ENCODING
4 33298 WORD LENGTH OPTIMIZATION//FIXED POINT ARITHMETIC//BITWIDTH
5 12738 SYNCHRONOUS DATAFLOW//DESIGN SPACE EXPLORATION//DATAFLOW GRAPHS
6 17996 STATE ASSIGNMENT//LOGIC SYNTHESIS//LOGIC OPTIMIZATION
7 10145 REGISTER ALLOCATION//INSTRUCTION SCHEDULING//INSTRUCTION LEVEL PARALLELISM
8 8485 RECONFIGURABLE COMPUTING//ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS//RECONFIGURABLE ARCHITECTURES
9 20981 SOFTWARE BASED SELF TEST//FUNCTIONAL VERIFICATION//POST SILICON VALIDATION
10 18911 SELF CHECKING CIRCUITS//ITERATIVE LOGIC ARRAYS//CONCURRENT ERROR DETECTION

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