Class information for:
Level 1: AMBITUS//CMOS TRANSISTOR NETWORKS//COMP BUSINESS GRP

Basic class information
Class id #P Avg. number of
references		 Database coverage
of references
25434 281 18.0 21%


Bar chart of Publication_year

Last years might be incomplete

Hierarchy of classes
The table includes all classes above and classes immediately below the current class.


Cluster id Level Cluster label #P
9 4 COMPUTER SCIENCE, THEORY & METHODS//COMPUTER SCIENCE, ARTIFICIAL INTELLIGENCE//COMPUTER SCIENCE, INFORMATION SYSTEMS 1247339
264 3       COMPUTER SCIENCE, HARDWARE & ARCHITECTURE//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//ENGINEERING, ELECTRICAL & ELECTRONIC 44494
752 2             JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//SOFT ERROR 12428
25434 1                   AMBITUS//CMOS TRANSISTOR NETWORKS//COMP BUSINESS GRP 281

Terms with highest relevance score


rank Term termType Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 AMBITUS authKW 217333 1% 100% 2
2 CMOS TRANSISTOR NETWORKS authKW 217333 1% 100% 2
3 COMP BUSINESS GRP address 217333 1% 100% 2
4 CORP PROD ENGN GRP address 217333 1% 100% 2
5 LEGAL SEQUENCE authKW 217333 1% 100% 2
6 LEGAL SEQUENCE NUMBER authKW 217333 1% 100% 2
7 MOS CIRCUIT authKW 217333 1% 100% 2
8 SWITCH LEVEL SIMULATION authKW 217333 1% 100% 2
9 TH CDMA authKW 217333 1% 100% 2
10 LOGIC SIMULATION authKW 200031 3% 20% 9

Web of Science journal categories


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 Computer Science, Hardware & Architecture 24130 52% 0% 146
2 Engineering, Electrical & Electronic 4188 70% 0% 197
3 Computer Science, Interdisciplinary Applications 3423 30% 0% 84
4 Computer Science, Software Engineering 817 13% 0% 36
5 COMPUTER APPLICATIONS & CYBERNETICS 658 1% 0% 4
6 Computer Science, Theory & Methods 328 10% 0% 28
7 Computer Science, Information Systems 126 6% 0% 17
8 Instruments & Instrumentation 11 3% 0% 8
9 Automation & Control Systems 7 1% 0% 4
10 Materials Science, Characterization, Testing 1 0% 0% 1

Address terms


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 COMP BUSINESS GRP 217333 1% 100% 2
2 CORP PROD ENGN GRP 217333 1% 100% 2
3 CNR CENS ITALIAN COUNCIL 108666 0% 100% 1
4 CNR E ORAZIONE NUMERALE SEGNALI 108666 0% 100% 1
5 INTEGRATED SYST COMP SYST 108666 0% 100% 1
6 PROCESSOR DESIGN 108666 0% 100% 1
7 SUPER TECN ELE ENGN 108666 0% 100% 1
8 TEST TECHNOL GRP 54332 0% 50% 1
9 INGN ELETTR GESTIONALE MECCAN 36221 0% 33% 1
10 SYST IC BUSINESS TEAM 36221 0% 33% 1

Journals


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 119477 26% 2% 73
2 IEEE DESIGN & TEST OF COMPUTERS 21595 5% 1% 14
3 MICROPROCESSING AND MICROPROGRAMMING 11718 4% 1% 11
4 JOURNAL OF DIGITAL SYSTEMS 11435 1% 5% 2
5 FUJITSU SCIENTIFIC & TECHNICAL JOURNAL 10049 3% 1% 8
6 DIGITAL PROCESSES 9054 0% 8% 1
7 INTEGRATION-THE VLSI JOURNAL 7030 3% 1% 8
8 JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 6448 3% 1% 8
9 SIMULATION 4574 2% 1% 6
10 IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS 4287 2% 1% 6

Author Key Words


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class		 LCSH search Wikipedia search
1 AMBITUS 217333 1% 100% 2 Search AMBITUS Search AMBITUS
2 CMOS TRANSISTOR NETWORKS 217333 1% 100% 2 Search CMOS+TRANSISTOR+NETWORKS Search CMOS+TRANSISTOR+NETWORKS
3 LEGAL SEQUENCE 217333 1% 100% 2 Search LEGAL+SEQUENCE Search LEGAL+SEQUENCE
4 LEGAL SEQUENCE NUMBER 217333 1% 100% 2 Search LEGAL+SEQUENCE+NUMBER Search LEGAL+SEQUENCE+NUMBER
5 MOS CIRCUIT 217333 1% 100% 2 Search MOS+CIRCUIT Search MOS+CIRCUIT
6 SWITCH LEVEL SIMULATION 217333 1% 100% 2 Search SWITCH+LEVEL+SIMULATION Search SWITCH+LEVEL+SIMULATION
7 TH CDMA 217333 1% 100% 2 Search TH+CDMA Search TH+CDMA
8 LOGIC SIMULATION 200031 3% 20% 9 Search LOGIC+SIMULATION Search LOGIC+SIMULATION
9 SWITCH LEVEL MODELING 144887 1% 67% 2 Search SWITCH+LEVEL+MODELING Search SWITCH+LEVEL+MODELING
10 ABIDING PATH 108666 0% 100% 1 Search ABIDING+PATH Search ABIDING+PATH

Core articles
The table includes core articles in the class. The following variables is taken into account for the relevance score of an article in a cluster c:
(1) Number of references referring to publications in the class.
(2) Share of total number of active references referring to publications in the class.
(3) Age of the article. New articles get higher score than old articles.
(4) Citation rate, normalized to year.


Rank Reference # ref.
in cl.		 Shr. of ref. in
cl.		 Citations
1 MAURER, PM , (2003) EFFICIENT EVENT-DRIVEN SIMULATION BY EXPLOITING THE OUTPUT OBSERVABILITY OF GATE CLUSTERS.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. VOL. 22. ISSUE 11. P. 1471 -1486 7 100% 2
2 BOSE, S , (2004) MODELING CUSTOM DIGITAL CIRCUITS FOR TEST.JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS. VOL. 20. ISSUE 6. P. 591 -609 10 63% 0
3 ZOLOTOREVICH, LA , YUKHNEVICH, DI , (1998) SWITCH-LEVEL VLSI QUASISTATIC SIMULATION METHODS: COMPARATIVE ACCURACY OF MODELS.AUTOMATION AND REMOTE CONTROL. VOL. 59. ISSUE 9. P. 1308 -1316 6 100% 0
4 HUANG, KC , LEE, CL , CHEN, JE , (1999) A COMPILED-CODE PARALLEL PATTERN LOGIC SIMULATOR WITH INERTIAL DELAY MODEL.JOURNAL OF INFORMATION SCIENCE AND ENGINEERING. VOL. 15. ISSUE 6. P. 885-897 5 100% 0
5 LI, M , HSIAO, MS , (2011) 3-D PARALLEL FAULT SIMULATION WITH GPGPU.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. VOL. 30. ISSUE 10. P. 1545 -1555 5 63% 6
6 LEE, YS , MAURER, PM , (1996) BIT-PARALLEL MULTIDELAY SIMULATION.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. VOL. 15. ISSUE 12. P. 1547-1554 5 100% 3
7 YANG, X , LIU, MY , (2000) CYCLE-BASED ALGORITHM USED TO ACCELERATE VHDL SIMULATION.JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY. VOL. 15. ISSUE 4. P. 383-387 4 100% 1
8 AISSI, C , GOBOVIC, D , (1998) REDUCTION OF COMPLEX MOS STRUCTURES IN SWITCH-LEVEL SIMULATORS.MICROELECTRONICS JOURNAL. VOL. 29. ISSUE 7. P. 431-439 4 100% 0
9 JONES, LG , (1992) AN INCREMENTAL ZERO INTEGER DELAY SWITCH-LEVEL SIMULATION ENVIRONMENT.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. VOL. 11. ISSUE 9. P. 1131-1139 5 100% 1
10 BOSE, S , NANDI, A , (2005) SCHEMATIC ARRAY MODELS FOR ASSOCIATIVE AND NON-ASSOCIATIVE MEMORY CIRCUITS.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. VOL. 24. ISSUE 10. P. 1582 -1593 5 63% 0

Classes with closest relation at Level 1


Rank Class id link
1 16623 TIME WARP//DISTRIBUTED SIMULATION//PARALLEL DISCRETE EVENT SIMULATION
2 1955 TEST DATA COMPRESSION//TRANSITION FAULTS//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
3 17444 REED MULLER EXPANSION//REED MULLER TRANSFORM//AND EXOR
4 18723 THEOREM PROVING//SYMBOLIC TRAJECTORY EVALUATION//MULTIWAY DECISION GRAPHS
5 14808 ORDERED BINARY DECISION DIAGRAMS//BINARY DECISION DIAGRAMS//BRANCHING PROGRAMS
6 5076 BUFFER INSERTION//CLOCK SKEW//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
7 18911 SELF CHECKING CIRCUITS//ITERATIVE LOGIC ARRAYS//CONCURRENT ERROR DETECTION
8 34708 MANEUVERING AFFORDANCE//RANDOMNESS BASED APPROACH//SATELLITE ROADWAY VEHICLE NETWORK
9 34716 CLIP7//CUSTOM LSI//PRIMAL DUAL METHOD FOR OPTIMIZATION
10 33569 ARBITRATION PROTOCOLS//3G MOBILE//ADAPTIVE ARBITER

Go to start page