Class information for:
Level 1: TECHNOLOGY MAPPING//FPGA ARCHITECTURE//FINE GRAIN RECONFIGURABLE VLSI

Basic class information
Class id #P Avg. number of
references		 Database coverage
of references
17471 597 21.0 30%


Bar chart of Publication_year

Last years might be incomplete

Hierarchy of classes
The table includes all classes above and classes immediately below the current class.


Cluster id Level Cluster label #P
9 4 COMPUTER SCIENCE, THEORY & METHODS//COMPUTER SCIENCE, ARTIFICIAL INTELLIGENCE//COMPUTER SCIENCE, INFORMATION SYSTEMS 1247339
264 3       COMPUTER SCIENCE, HARDWARE & ARCHITECTURE//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//ENGINEERING, ELECTRICAL & ELECTRONIC 44494
470 2             COMPUTER SCIENCE, HARDWARE & ARCHITECTURE//IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS//NETWORK ON CHIP 15913
17471 1                   TECHNOLOGY MAPPING//FPGA ARCHITECTURE//FINE GRAIN RECONFIGURABLE VLSI 597

Terms with highest relevance score


rank Term termType Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 TECHNOLOGY MAPPING authKW 513430 5% 31% 32
2 FPGA ARCHITECTURE authKW 364037 2% 65% 11
3 FINE GRAIN RECONFIGURABLE VLSI authKW 306881 1% 100% 6
4 ROUTABILITY authKW 210417 2% 34% 12
5 FIELD PROGRAMMABLE GATE ARRAY FPGA ARCHITECTURE authKW 204587 1% 100% 4
6 FPGA TESTING authKW 204587 1% 100% 4
7 FPGA authKW 203094 17% 4% 100
8 STRUCTURED ASIC authKW 184124 1% 60% 6
9 FIELD PROGRAMMABLE GATE ARRAYS FPGAS authKW 173328 6% 10% 34
10 SEGMENTED CHANNEL authKW 163668 1% 80% 4

Web of Science journal categories


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 Computer Science, Hardware & Architecture 67631 60% 0% 356
2 Engineering, Electrical & Electronic 7924 66% 0% 396
3 Computer Science, Software Engineering 2842 16% 0% 97
4 Computer Science, Interdisciplinary Applications 1805 15% 0% 91
5 Computer Science, Theory & Methods 1113 12% 0% 74
6 Computer Science, Information Systems 839 10% 0% 61
7 Logic 48 1% 0% 4
8 Automation & Control Systems 36 2% 0% 12
9 Computer Science, Artificial Intelligence 31 3% 0% 15
10 Nanoscience & Nanotechnology 25 3% 0% 19

Address terms


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 DESIGN AUTOMAT TEST 102294 0% 100% 2
2 ELE OINFORMAT GRP 102294 0% 100% 2
3 EMBEDDED SYST ON CHIP GRP 102294 0% 100% 2
4 SYST LEVEL INTEGRAT GRP 92062 1% 60% 3
5 FPGA SOFTWARE CORE GRP 76717 1% 50% 3
6 SYST PROGRAMMABLE CHIP 68194 0% 67% 2
7 ADV PROP SYST GRP 51147 0% 100% 1
8 ASICS GRP 51147 0% 100% 1
9 COM SCI SYST ENGN 51147 0% 100% 1
10 COMBINATOR OPTIMIZAT MC 6056 51147 0% 100% 1

Journals


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 73989 12% 2% 70
2 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 72622 14% 2% 83
3 ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 68401 3% 8% 17
4 ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 42292 4% 3% 25
5 JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 13704 3% 2% 17
6 IET COMPUTERS AND DIGITAL TECHNIQUES 9550 2% 2% 9
7 VLSI DESIGN 9292 2% 2% 9
8 IEEE DESIGN & TEST OF COMPUTERS 7454 2% 1% 12
9 IEEE TRANSACTIONS ON COMPUTERS 7179 5% 1% 27
10 IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 6066 2% 1% 9

Author Key Words


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class		 LCSH search Wikipedia search
1 TECHNOLOGY MAPPING 513430 5% 31% 32 Search TECHNOLOGY+MAPPING Search TECHNOLOGY+MAPPING
2 FPGA ARCHITECTURE 364037 2% 65% 11 Search FPGA+ARCHITECTURE Search FPGA+ARCHITECTURE
3 FINE GRAIN RECONFIGURABLE VLSI 306881 1% 100% 6 Search FINE+GRAIN+RECONFIGURABLE+VLSI Search FINE+GRAIN+RECONFIGURABLE+VLSI
4 ROUTABILITY 210417 2% 34% 12 Search ROUTABILITY Search ROUTABILITY
5 FIELD PROGRAMMABLE GATE ARRAY FPGA ARCHITECTURE 204587 1% 100% 4 Search FIELD+PROGRAMMABLE+GATE+ARRAY+FPGA+ARCHITECTURE Search FIELD+PROGRAMMABLE+GATE+ARRAY+FPGA+ARCHITECTURE
6 FPGA TESTING 204587 1% 100% 4 Search FPGA+TESTING Search FPGA+TESTING
7 FPGA 203094 17% 4% 100 Search FPGA Search FPGA
8 STRUCTURED ASIC 184124 1% 60% 6 Search STRUCTURED+ASIC Search STRUCTURED+ASIC
9 FIELD PROGRAMMABLE GATE ARRAYS FPGAS 173328 6% 10% 34 Search FIELD+PROGRAMMABLE+GATE+ARRAYS+FPGAS Search FIELD+PROGRAMMABLE+GATE+ARRAYS+FPGAS
10 SEGMENTED CHANNEL 163668 1% 80% 4 Search SEGMENTED+CHANNEL Search SEGMENTED+CHANNEL

Core articles
The table includes core articles in the class. The following variables is taken into account for the relevance score of an article in a cluster c:
(1) Number of references referring to publications in the class.
(2) Share of total number of active references referring to publications in the class.
(3) Age of the article. New articles get higher score than old articles.
(4) Citation rate, normalized to year.


Rank Reference # ref.
in cl.		 Shr. of ref. in
cl.		 Citations
1 RUAN, AW , HUANG, HY , WANG, JW , ZHAO, YF , (2016) A ROUTABILITY-AWARE ALGORITHM FOR BOTH GLOBAL AND LOCAL INTERCONNECT RESOURCE TEST AND DIAGNOSIS OF XILINX SRAM-FPGAS.JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS. VOL. 32. ISSUE 6. P. 749 -762 12 92% 0
2 GUPTE, A , VYAS, S , JONES, PH , (2015) A FAULT-AWARE TOOLCHAIN APPROACH FOR FPGA FAULT TOLERANCE.ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS. VOL. 20. ISSUE 2. P. - 15 65% 0
3 DOUMAR, A , ITO, H , (2003) DETECTING, DIAGNOSING, AND TOLERATING FAULTS IN SRAM-BASED FIELD PROGRAMMABLE GATE ARRAYS: A SURVEY.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. VOL. 11. ISSUE 3. P. 386 -405 15 79% 23
4 RUAN, AW , JIE, BR , WAN, L , YANG, JH , XIANG, CY , ZHU, ZJ , WANG, Y , (2014) A BITSTREAM READBACK-BASED AUTOMATIC FUNCTIONAL TEST AND DIAGNOSIS METHOD FOR XILINX FPGAS.MICROELECTRONICS RELIABILITY. VOL. 54. ISSUE 8. P. 1627 -1635 9 100% 1
5 ZHANG, DH , LI, W , DU, T , (2015) A MULTILEVEL PSEUDO-BOOLEAN SATISFIABILITY-BASED APPROACH FOR SEGMENTED CHANNEL ROUTING.JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS. VOL. 24. ISSUE 6. P. - 10 83% 0
6 FAN, HB , LIU, JP , WU, YL , CHEUNG, CC , (2003) ON OPTIMAL HYPERUNIVERSAL AND REARRANGEABLE SWITCH BOX DESIGNS.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. VOL. 22. ISSUE 12. P. 1637-1649 11 100% 8
7 MUTUKUDA, O , YE, A , KHAN, G , (2012) UTILIZING MULTI-BIT CONNECTIONS TO IMPROVE THE AREA EFFICIENCY OF UNIDIRECTIONAL ROUTING RESOURCES FOR ROUTING MULTI-BIT SIGNALS ON FPGAS.MICROPROCESSORS AND MICROSYSTEMS. VOL. 36. ISSUE 3. P. 167 -175 8 100% 0
8 SEDCOLE, P , CHEUNG, P , STOTT, E , (2010) FAULT TOLERANCE AND RELIABILITY IN FIELD-PROGRAMMABLE GATE ARRAYS.IET COMPUTERS AND DIGITAL TECHNIQUES. VOL. 4. ISSUE 3. P. 196 -210 12 67% 8
9 PARRIS, MG , SHARMA, CA , DEMARA, RF , (2011) PROGRESS IN AUTONOMOUS FAULT RECOVERY OF FIELD PROGRAMMABLE GATE ARRAYS.ACM COMPUTING SURVEYS. VOL. 43. ISSUE 4. P. - 10 77% 7
10 WANG, D , YANG, HG , XIE, XH , FAN, DR , WANG, F , (2016) ON-CHIP GENERATING FPGA TEST CONFIGURATION BITSTREAMS TO REDUCE MANUFACTURING TEST TIME.CHINESE JOURNAL OF ELECTRONICS. VOL. 25. ISSUE 1. P. 64 -70 7 100% 0

Classes with closest relation at Level 1


Rank Class id link
1 8485 RECONFIGURABLE COMPUTING//ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS//RECONFIGURABLE ARCHITECTURES
2 24020 DEFECT TOLERANCE//NEUROMORPHIC NETWORKS//CMOL
3 17996 STATE ASSIGNMENT//LOGIC SYNTHESIS//LOGIC OPTIMIZATION
4 11639 FLOORPLANNING//PLACEMENT//PHYSICAL DESIGN
5 15984 POWER ESTIMATION//SWITCHING ACTIVITY//BUS ENCODING
6 17794 STEINER TREE//GLOBAL ROUTING//STEINER MINIMAL TREE
7 13388 CHANNEL ROUTING//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//VLSI LAYOUT
8 18911 SELF CHECKING CIRCUITS//ITERATIVE LOGIC ARRAYS//CONCURRENT ERROR DETECTION
9 17003 EVOLVABLE HARDWARE//LOG SYST//EMBRYONICS
10 30433 RETIMING//CLOCK SCHEDULING//SEMI SYNCHRONOUS CIRCUIT

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