Class information for:
Level 1: CHANNEL ROUTING//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//VLSI LAYOUT

Basic class information
Class id #P Avg. number of
references		 Database coverage
of references
13388 841 17.1 28%


Bar chart of Publication_year

Last years might be incomplete

Hierarchy of classes
The table includes all classes above and classes immediately below the current class.


Cluster id Level Cluster label #P
9 4 COMPUTER SCIENCE, THEORY & METHODS//COMPUTER SCIENCE, ARTIFICIAL INTELLIGENCE//COMPUTER SCIENCE, INFORMATION SYSTEMS 1247339
377 3       TOPOLOGY OPTIMIZATION//STRUCTURAL AND MULTIDISCIPLINARY OPTIMIZATION//LATTICE RULES 32367
2712 2             IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//PHYSICAL DESIGN//FLOORPLANNING 3318
13388 1                   CHANNEL ROUTING//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//VLSI LAYOUT 841

Terms with highest relevance score


rank Term termType Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 CHANNEL ROUTING authKW 801651 4% 60% 37
2 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS journal 403232 28% 5% 232
3 VLSI LAYOUT authKW 376928 3% 36% 29
4 PIN ASSIGNMENT authKW 259330 1% 71% 10
5 LAYER ASSIGNMENT authKW 235982 2% 50% 13
6 ESCAPE ROUTING authKW 193632 1% 67% 8
7 OVER THE CELL ROUTING authKW 186720 1% 86% 6
8 SINGLE ROW ROUTING authKW 186720 1% 86% 6
9 VIA MINIMIZATION authKW 161726 1% 64% 7
10 CELL SYNTHESIS authKW 151277 1% 83% 5

Web of Science journal categories


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 Computer Science, Hardware & Architecture 64784 49% 0% 414
2 Engineering, Electrical & Electronic 9632 62% 0% 520
3 Computer Science, Interdisciplinary Applications 9476 29% 0% 242
4 Computer Science, Theory & Methods 2704 16% 0% 135
5 COMPUTER APPLICATIONS & CYBERNETICS 1370 1% 0% 10
6 Computer Science, Software Engineering 1109 9% 0% 74
7 Mathematics, Applied 511 11% 0% 92
8 Computer Science, Information Systems 466 7% 0% 56
9 Logic 143 1% 0% 8
10 Computer Science, Artificial Intelligence 28 2% 0% 18

Address terms


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 IND POWER 48408 0% 67% 2
2 ADV IC DESIGN SIMULAT 36307 0% 100% 1
3 ASSOC COMPUTACAO LICADA 36307 0% 100% 1
4 ATD GRP 36307 0% 100% 1
5 CLV B3 36307 0% 100% 1
6 COMP ENGN MICROELE 36307 0% 100% 1
7 COMP ROBOT SYST 36307 0% 100% 1
8 DISCS 36307 0% 100% 1
9 FRA AS N 36307 0% 100% 1
10 HBEREICH 10 INFORMAT 36307 0% 100% 1

Journals


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 403232 28% 5% 232
2 INTEGRATION-THE VLSI JOURNAL 111171 7% 6% 55
3 JOURNAL OF DIGITAL SYSTEMS 34386 1% 16% 6
4 VLSI SYSTEMS DESIGN 15693 0% 11% 4
5 IEEE DESIGN & TEST OF COMPUTERS 11907 2% 2% 18
6 VLSI DESIGN 11725 1% 3% 12
7 IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 10422 2% 2% 14
8 JOURNAL OF VLSI AND COMPUTER SYSTEMS 9073 0% 13% 2
9 ALGORITHMICA 8367 3% 1% 23
10 IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES 5310 1% 2% 9

Author Key Words


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class		 LCSH search Wikipedia search
1 CHANNEL ROUTING 801651 4% 60% 37 Search CHANNEL+ROUTING Search CHANNEL+ROUTING
2 VLSI LAYOUT 376928 3% 36% 29 Search VLSI+LAYOUT Search VLSI+LAYOUT
3 PIN ASSIGNMENT 259330 1% 71% 10 Search PIN+ASSIGNMENT Search PIN+ASSIGNMENT
4 LAYER ASSIGNMENT 235982 2% 50% 13 Search LAYER+ASSIGNMENT Search LAYER+ASSIGNMENT
5 ESCAPE ROUTING 193632 1% 67% 8 Search ESCAPE+ROUTING Search ESCAPE+ROUTING
6 OVER THE CELL ROUTING 186720 1% 86% 6 Search OVER+THE+CELL+ROUTING Search OVER+THE+CELL+ROUTING
7 SINGLE ROW ROUTING 186720 1% 86% 6 Search SINGLE+ROW+ROUTING Search SINGLE+ROW+ROUTING
8 VIA MINIMIZATION 161726 1% 64% 7 Search VIA+MINIMIZATION Search VIA+MINIMIZATION
9 CELL SYNTHESIS 151277 1% 83% 5 Search CELL+SYNTHESIS Search CELL+SYNTHESIS
10 PACKAGE ROUTING 145228 0% 100% 4 Search PACKAGE+ROUTING Search PACKAGE+ROUTING

Core articles
The table includes core articles in the class. The following variables is taken into account for the relevance score of an article in a cluster c:
(1) Number of references referring to publications in the class.
(2) Share of total number of active references referring to publications in the class.
(3) Age of the article. New articles get higher score than old articles.
(4) Citation rate, normalized to year.


Rank Reference # ref.
in cl.		 Shr. of ref. in
cl.		 Citations
1 MAREK-SADOWSKA, M , (2016) AUTOMATED ROUTING FOR VLSI: KUH'S GROUP CONTRIBUTIONS.IEEE CIRCUITS AND SYSTEMS MAGAZINE. VOL. 16. ISSUE 2. P. 35 -49 21 57% 0
2 DAS, S , SUR-KOLAY, S , BHATTACHARYA, BB , (2004) MANHATTAN-DIAGONAL ROUTING IN CHANNELS AND SWITCHBOXES.ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS. VOL. 9. ISSUE 1. P. 75 -104 14 100% 1
3 LAPAUGH, AS , PINTER, RY , (1989) CHANNEL ROUTING FOR INTEGRATED-CIRCUITS.ANNUAL REVIEW OF COMPUTER SCIENCE. VOL. 4. ISSUE . P. 307 -363 26 93% 1
4 RECSKI, A , (2001) SOME POLYNOMIALLY SOLVABLE SUBCASES OF THE DETAILED ROUTING PROBLEM IN VLSI DESIGN.DISCRETE APPLIED MATHEMATICS. VOL. 115. ISSUE 1-3. P. 199-208 15 88% 1
5 HSIAO, PY , (1996) NEARLY BALANCED QUAD LIST QUAD TREE - A DATA STRUCTURE FOR VLSI LAYOUT SYSTEMS.VLSI DESIGN. VOL. 4. ISSUE 1. P. 17-32 15 100% 0
6 TAN, XH , SONG, XY , (1999) ROUTING MULTITERMINAL NETS ON A HEXAGONAL GRID.DISCRETE APPLIED MATHEMATICS. VOL. 90. ISSUE 1-3. P. 245-255 13 100% 1
7 GONZALEZ, TF , ZHENG, SQ , (1998) ON ENSURING MULTILAYER WIRABILITY BY STRETCHING LAYOUTS.VLSI DESIGN. VOL. 7. ISSUE 4. P. 365-383 13 100% 1
8 KUCHEM, R , WAGNER, D , WAGNER, F , (1996) OPTIMIZING AREA FOR THREE-LAYER KNOCK-KNEE CHANNEL ROUTING.ALGORITHMICA. VOL. 15. ISSUE 5. P. 495-519 14 100% 0
9 CHEN, HS , LEE, DT , (2000) A FASTER ONE-DIMENSIONAL TOPOLOGICAL COMPACTION ALGORITHM WITH JOG INSERTION.ALGORITHMICA. VOL. 28. ISSUE 4. P. 390 -421 13 87% 1
10 FUNABIKI, N , NISHIKAWA, S , (1997) A NEURAL NETWORK APPROACH FOR MULTILAYER OVER-THE-CELL CHANNEL ROUTING PROBLEMS.NEUROCOMPUTING. VOL. 16. ISSUE 4. P. 319-332 15 83% 0

Classes with closest relation at Level 1


Rank Class id link
1 17794 STEINER TREE//GLOBAL ROUTING//STEINER MINIMAL TREE
2 11639 FLOORPLANNING//PLACEMENT//PHYSICAL DESIGN
3 34716 CLIP7//CUSTOM LSI//PRIMAL DUAL METHOD FOR OPTIMIZATION
4 25074 SONET RING//RING LOADING PROBLEM//ETHERNET RING PROTECTION
5 17471 TECHNOLOGY MAPPING//FPGA ARCHITECTURE//FINE GRAIN RECONFIGURABLE VLSI
6 17996 STATE ASSIGNMENT//LOGIC SYNTHESIS//LOGIC OPTIMIZATION
7 25434 AMBITUS//CMOS TRANSISTOR NETWORKS//COMP BUSINESS GRP
8 27160 RAINBOW CONNECTION NUMBER//RAINBOW CONNECTION//RAINBOW PATH
9 24819 TIGHT SPAN//INJECTIVE HULL//Q HYPERCONVEX
10 12116 SIMULATED ANNEALING//EXTREMAL OPTIMIZATION//ADAPTIVE COOLING SCHEDULE

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