Class information for:
Level 1: CLOCK AND DATA RECOVERY CDR//DELAY LOCKED LOOP DLL//SERIAL LINK

Basic class information
Class id #P Avg. number of
references		 Database coverage
of references
5509 1613 13.6 52%


Bar chart of Publication_year

Last years might be incomplete

Hierarchy of classes
The table includes all classes above and classes immediately below the current class.


Cluster id Level Cluster label #P
20 4 PHYSICS, NUCLEAR//PHYSICS, PARTICLES & FIELDS//PHYSICAL REVIEW C 270246
544 3       IEEE JOURNAL OF SOLID-STATE CIRCUITS//ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING//IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 18576
2364 2             IEEE JOURNAL OF SOLID-STATE CIRCUITS//TIME TO DIGITAL CONVERTER TDC//CLOCK AND DATA RECOVERY CDR 4334
5509 1                   CLOCK AND DATA RECOVERY CDR//DELAY LOCKED LOOP DLL//SERIAL LINK 1613

Terms with highest relevance score


rank Term termType Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 CLOCK AND DATA RECOVERY CDR authKW 1143836 5% 73% 83
2 DELAY LOCKED LOOP DLL authKW 917255 5% 65% 74
3 SERIAL LINK authKW 876636 4% 75% 62
4 CLOCK AND DATA RECOVERY authKW 793847 4% 71% 59
5 DELAY LOCKED LOOP authKW 679979 4% 58% 62
6 IEEE JOURNAL OF SOLID-STATE CIRCUITS journal 608245 32% 6% 514
7 JITTER TOLERANCE authKW 551234 2% 94% 31
8 DLL authKW 417229 2% 57% 39
9 FAST LOCKING authKW 363429 1% 80% 24
10 PHASE LOCKED LOOP PLL authKW 344001 6% 18% 100

Web of Science journal categories


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with term
in class
1 Engineering, Electrical & Electronic 44800 95% 0% 1526
2 Computer Science, Hardware & Architecture 8387 13% 0% 210
3 Telecommunications 341 4% 0% 72
4 Computer Science, Information Systems 48 2% 0% 33
5 Nanoscience & Nanotechnology 27 2% 0% 39
6 Computer Science, Software Engineering 7 1% 0% 16
7 Instruments & Instrumentation 2 1% 0% 20
8 Engineering, Manufacturing 0 0% 0% 6
9 Optics 0 2% 0% 28
10 Physics, Applied -0 3% 0% 56

Address terms


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 DRAM DESIGN 95821 1% 56% 9
2 DRAM DESIGN TEAM 57679 0% 38% 8
3 DRAM DESIGN TEAM 2 37858 0% 100% 2
4 MIXED SIGNAL INTEGRATED CIRCUIT DESIGN 37858 0% 100% 2
5 SERDES TECHNOL GRP 37858 0% 100% 2
6 SOLID STATE CIRCUIT 37858 0% 100% 2
7 SEMICOND CAD 34070 0% 60% 3
8 GR H DESIGN TEAM 25237 0% 67% 2
9 SAMSUNG RFIC DESIGN 25237 0% 67% 2
10 STATE ASIC 25237 0% 67% 2

Journals


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class
1 IEEE JOURNAL OF SOLID-STATE CIRCUITS 608245 32% 6% 514
2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 89317 8% 3% 137
3 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 43796 7% 2% 111
4 ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 35698 5% 3% 74
5 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 33910 5% 2% 78
6 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 29317 2% 5% 29
7 IEICE TRANSACTIONS ON ELECTRONICS 18161 5% 1% 76
8 IEICE ELECTRONICS EXPRESS 12367 3% 2% 42
9 IET CIRCUITS DEVICES & SYSTEMS 8669 1% 3% 16
10 ELECTRONICS LETTERS 8166 8% 0% 131

Author Key Words


Rank Term Chi square Shr. of publ. in
class containing
term		 Class's shr. of
term's tot. occurrences		 #P with
term in
class		 LCSH search Wikipedia search
1 CLOCK AND DATA RECOVERY CDR 1143836 5% 73% 83 Search CLOCK+AND+DATA+RECOVERY+CDR Search CLOCK+AND+DATA+RECOVERY+CDR
2 DELAY LOCKED LOOP DLL 917255 5% 65% 74 Search DELAY+LOCKED+LOOP+DLL Search DELAY+LOCKED+LOOP+DLL
3 SERIAL LINK 876636 4% 75% 62 Search SERIAL+LINK Search SERIAL+LINK
4 CLOCK AND DATA RECOVERY 793847 4% 71% 59 Search CLOCK+AND+DATA+RECOVERY Search CLOCK+AND+DATA+RECOVERY
5 DELAY LOCKED LOOP 679979 4% 58% 62 Search DELAY+LOCKED+LOOP Search DELAY+LOCKED+LOOP
6 JITTER TOLERANCE 551234 2% 94% 31 Search JITTER+TOLERANCE Search JITTER+TOLERANCE
7 DLL 417229 2% 57% 39 Search DLL Search DLL
8 FAST LOCKING 363429 1% 80% 24 Search FAST+LOCKING Search FAST+LOCKING
9 PHASE LOCKED LOOP PLL 344001 6% 18% 100 Search PHASE+LOCKED+LOOP+PLL Search PHASE+LOCKED+LOOP+PLL
10 HIGH SPEED I O 266645 1% 78% 18 Search HIGH+SPEED+I+O Search HIGH+SPEED+I+O

Core articles
The table includes core articles in the class. The following variables is taken into account for the relevance score of an article in a cluster c:
(1) Number of references referring to publications in the class.
(2) Share of total number of active references referring to publications in the class.
(3) Age of the article. New articles get higher score than old articles.
(4) Citation rate, normalized to year.


Rank Reference # ref.
in cl.		 Shr. of ref. in
cl.		 Citations
1 YUAN, F , AL-TAEE, AR , YE, A , SADR, S , (2014) DESIGN TECHNIQUES FOR DECISION FEEDBACK EQUALISATION OF MULTI-GIGA-BIT-PER-SECOND SERIAL DATA LINKS: A STATE-OF-THE-ART REVIEW.IET CIRCUITS DEVICES & SYSTEMS. VOL. 8. ISSUE 2. P. 118-130 43 93% 0
2 AL-TAEE, AR , YUAN, F , YE, AG , SADR, S , (2014) NEW 2-D EYE-OPENING MONITOR FOR GB/S SERIAL LINKS.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. VOL. 22. ISSUE 6. P. 1209 -1218 30 97% 1
3 WANG, W , BUCKWALTER, JF , (2016) SOURCE CODING AND PREEMPHASIS FOR DOUBLE-EDGED PULSEWIDTH MODULATION SERIAL COMMUNICATION.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. VOL. 24. ISSUE 2. P. 555 -566 26 90% 0
4 KWAK, YH , KIM, Y , HWANG, S , KIM, C , (2013) A 20 GB/S CLOCK AND DATA RECOVERY WITH A PING-PONG DELAY LINE FOR UNLIMITED PHASE SHIFTING IN 65 NM CMOS PROCESS.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS. VOL. 60. ISSUE 2. P. 303-313 20 100% 3
5 WU, GY , HUANG, DP , LI, JX , GUI, P , LIU, TW , GUO, ST , WANG, R , FAN, YL , CHAKRABORTY, S , MORGAN, M , (2016) A 1-16 GB/S ALL-DIGITAL CLOCK AND DATA RECOVERY WITH A WIDEBAND HIGH-LINEARITY PHASE INTERPOLATOR.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. VOL. 24. ISSUE 7. P. 2511 -2520 20 91% 0
6 CHEN, MS , YANG, CKK , (2015) A 50-64 GB/S SERIALIZING TRANSMITTER WITH A 4-TAP, LC-LADDER-FILTER-BASED FFE IN 65 NM CMOS TECHNOLOGY.IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 50. ISSUE 8. P. 1903 -1916 20 87% 3
7 HASSANI, M , SAEEDI, S , (2015) EDGE-COMBINING MULTI-PHASE DLL FREQUENCY MULTIPLIER WITH REDUCED STATIC PHASE OFFSET AND LINEARIZED DELAY TRANSFER CURVE.ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING. VOL. 82. ISSUE 3. P. 705 -718 24 75% 0
8 GHOLAMI, M , RAHIMPOUR, H , ARDESHIR, G , MIARNAIMI, H , (2014) DIGITAL DELAY LOCKED LOOP-BASED FREQUENCY SYNTHESISER FOR DIGITAL VIDEO BROADCASTING-TERRESTRIAL RECEIVERS.IET CIRCUITS DEVICES & SYSTEMS. VOL. 8. ISSUE 1. P. 38-46 19 95% 2
9 SHU, GH , SAXENA, S , CHOI, WS , TALEGAONKAR, M , INTI, R , ELSHAZLY, A , YOUNG, B , HANUMOLU, PK , (2014) A REFERENCE-LESS CLOCK AND DATA RECOVERY CIRCUIT USING PHASE-ROTATING PHASE-LOCKED LOOP.IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 49. ISSUE 4. P. 1036-1047 18 95% 7
10 MIN, B , YANG, NHW , PALERMO, S , (2016) 10 GB/S ADAPTIVE RECEIVE-SIDE MERGED NEAR-END AND FAR-END CROSSTALK CANCELLATION CIRCUITRY IN 65 NM CMOS.ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING. VOL. 88. ISSUE 2. P. 233 -243 19 90% 0

Classes with closest relation at Level 1


Rank Class id link
1 9859 TIME TO DIGITAL CONVERTER TDC//DIGITALLY CONTROLLED OSCILLATOR DCO//TIME TO DIGITAL CONVERTER
2 26925 BURST MODE RECEIVER//BURST MODE//GATED OSCILLATOR
3 2137 PHASE NOISE//VOLTAGE CONTROLLED OSCILLATOR VCO//VCO
4 15603 DECISION CIRCUITS//MODULATOR DRIVER//OPTICAL MODULATOR DRIVER
5 16298 TRANSIMPEDANCE AMPLIFIER//TRANSIMPEDANCE AMPLIFIER TIA//OPTICAL RECEIVERS
6 15732 WIRELESS INTERCONNECT//SUPERREGENERATIVE RECEIVER//PULSE GENERATOR
7 17149 SUBSTRATE NOISE//SUBSTRATE COUPLING//POWER SUPPLY NOISE
8 26058 SYNCHRONOUS STATE//DOUBLE FREQUENCY JITTER//WAITING TIME JITTER
9 4435 PIPELINED ADC//ANALOG TO DIGITAL CONVERTER ADC//SAR ADC
10 11170 SIMULTANEOUS SWITCHING NOISE//SIMULTANEOUS SWITCHING NOISE SSN//SIGNAL INTEGRITY

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