In this course we study in detail all the necessary phenomena relating to logic value changes inside the logic circuit with emphasis on advanced nanoscale phenomena. The key issues in this course are to understand the nature of performance parameters such as silicon area, speed and power consumption. The structure and contents are quite similar to VLSI design courses given at many universities. The main difference is in nanoscale phenomena and bringing up power consumption issues.
This course aims to analyze and design digital integrated circuits with advanced full cus-tom and standard cell techniques based on nanoscale CMOS. We emphasize the key new phenomena and design solutions adopted to handle nanoscale phenomena at circuit and micro architecture level.
Syllabus
Review of the IC development trends. The future of IC technologies is discussed. The technology scaling models and new device level phenomena of deep submicron MOS transistors is presented.
Review of the MOS transistor physics and device model, especially the key submicron device phenomena relevant to the VLSI circuit operations
A very simplified CMOS process flow is introduced. Nanoscale CMOS issues to circuit layouts and floorplans are presented
CMOS logic from power and performance perspective are analyzed.
Power consumption in CMOS and leakage power as well as voltage scaling issues are described
Performance optimizention through micro architecture design for data paths are described
Sequential logic circuit, registers, timing and clock distribution challenge are analyzed in modern CMOS circuits
Circuit techniques for data path structures are described. Different adder and multiplier implementation schemes are introduced. Pipelining is introduced. Impact of the Vdd scaling and associated pipelining and parallelization techniques for the reduction of the data path power consumption are described.
Metal wires and interconnect as design objects are described.
Variability reduction and design optimization techniques are introduced.
Memory and Network-on-Chip architectures .