FIL3111 Advanced Topics in SOC Design 7.5 credits

1. Requirements Analysis for ASIC Design, Implementation and Verificaiton

2. Modeling as efficient RTL

3. Able to control and write complex Logic and Physical Synthesis Scripts

4. Perform Static Timing and Power Analysis

5. Verification using constraint stimuli generation and assertions

6. Apply the above to a complex real life example assigned by the examiner related to the PhD topic of the student

1. To be able to analyze the functional requirements 

2. Dimension a system in terms of RTL blocks

3. Design Verification Plan and architect complex test benches

4. Master constrained based stimuli generation and formal assertions

5. Perform Logic and Physical synthesis 

6. Analyze timing and power for complex SOC functionalities

7. Analyze verification reports to check for coverage

Admitted as doctoral student

Background in CMOS, Digital Design, HDL and Verification

Synopsys, Cadence and Mentor EDA Tools

IL2225 Lecture Slides or IL2450 Lectures

If the course is discontinued, students may request to be examined during the following two academic years.

• EXA1 - Examination, 7.5 credits, grading scale: P, F

Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.

The examiner may apply another examination format when re-examining individual students.

Same written exam and lab as IL2225 or IL2450

Complex Project Example assigned by the Examiner

Clearing the IL2225 or IL2450 exam and labs

Satisfactory completion of the Project Example assigned by the Examiner

Ahmed Hemani

• All members of a group are responsible for the group's work.
• In any assessment, every student shall honestly disclose any help received and sources used.
• In an oral assessment, every student shall be able to present and answer questions about the entire assignment and solution.