PhD Waqar Ahmad

Where are you from and where did you study before coming to School of ICT?

– I am from Pakistan. I got Masters in Electrical Engineering from University of Engineering and Technology Taxila, Pakistan, before coming to School of ICT.

What is your topic and why did you choose it?

– My topic is study and analysis of On-Chip core switching noise for 3D stacked Power Distribution Networks. 3D integration is an attractive option owing to drop across long power distribution rails in conventional 2D integration during switching of on-chip load. However, power integrity is the main issue for the design of high computing 3D integrated chips. I chose this topic because 3D IC is the best alternative to present time SoC, specifically for mixed applications of analog and digital. 3D integration also offers small form factor and large bandwidth.

Describe your topic in short

– 2D integration is fabricating the transistors in XY-plane, which requires a large area compared to 3D integration where transistors are fabricated in different layers using the third dimension like a tower, which covers less area. Supplying power to 3D stacked ICs is like supplying water to a multi-story building, which requires huge pumping power, compared to a single story large complex. Core switching is like if water taps are opened at various floors of multi-story building, then it is difficult to maintain the water pressure. Keep in mind that a storage tank can only be placed at the base of the multi-story building in this case. Power integrity for 3D ICs means to maintain water pressure at each floor of the building under worst conditions.

Tell me something about your results 

– Compact, fast, and accurate Mathematical models have been developed for early estimation of the core switching noise for 3D power distribution networks. These models help early design tradeoffs for 3D power distribution networks. Mathematical models for the design of on-chip decoupling capacitance for 3D power distribution networks have also been proposed. The results have been published in IEEE transactions and IEEE conferences.

What will the future bring for your research topic?

– I think 3D integration is the future of modern high speed electronics, specifically for hand held devices and high computing systems. Power integrity is the main bottleneck for 3D ICs design. Mathematical models proposed during the research can be used for the development of power integrity tools for 3D power distribution networks in future.

What are your plans for the future?

– I will be more than happy to stay in Sweden if I find some job to continue my research. Otherwise, I will go back to Pakistan and keep up the research ties with KTH in future.