The course teaches digital systems design and verificaiton using hardware description language. Additionally, the course includes simulation and synthesis of digital systems designs targeting FPGAs.
- Review of elementary digital design concepts and their modeling and verification in HDL.
- Review of sequential elements, timing concepts, and their applications and modelling and verification in HDL.
- Design of finite state machines (FSMs) and datapaths.
- Modeling and verification of FSM and datapaths in HDL.
- Advanced digital systems concepts.
- Advanced verification concepts: constrained random stimuli generation, assertions, coverage, formal verification.