Hoppa till huvudinnehållet
Till KTH:s startsida

IH2659 Nanofabrication Technologies 7,5 hp

Course memo Autumn 2024-10130...

Version 3 – 09/21/2024, 11:38:24 AM

Course offering

Autumn 2024-10130 (Start date 28 Oct 2024, English)
Autumn 2024-50772 (Start date 28 Oct 2024, English)

Language Of Instruction

English

Offered By

EECS/Electrical Engineering

Course memo Autumn 2024

Headings denoted with an asterisk ( * ) is retrieved from the course syllabus version Autumn 2023

Content and learning outcomes

Course contents

The course covers process technologies that are used in micro- and nanofabrication of devices and systems on wafers. Applications include all technologies that are based on wafer scale fabrication such as integrated circuits, micro-electro-mechanical systems and optical devices. The basic unit processes deposition, patterning, etching, doping and heat treatment are covered, followed by process integration to build complex devices including statistical process control and yield models. Moore's law and the basic economics for integrated circuits are covered and examplified by reviewing the state-of-the art process technology nodes. Hands-on experience of fabricating devices in a clean room (Electrum Laboratory) and use a number of unit processes included in the course.

The course gives the student basic understanding of the sustainability aspects in integrated circuit fabrication.

Intended learning outcomes

After the course, the student should be able to

  • discuss and review unit manufacturing processes for micro- and nanofabrication on wafers
  • discuss and review Moore's law and advanced process technologies
  • discuss and review examples of process integration
  • use models and calculate relevant characteristics and conditions in process technology
  • fabricate devices in a clean room.

Learning activities

16 lectures
1 laboration in Electrum Laboratory
2 home assigments

Detailed plan

Lecture 1: Introduction to course and subject, review of CMOS circuit and technology (Chapter 1)
Lecture 2: Planar technology, key process innovations, Moore's law, KTH FDSOI technology (Chapter 2)
Lecture 3: Crystals, defects, doping and semiconductor wafers (Chapter 3)
Lecture 4: Semiconductor Manufacturing, Cleanrooms and Yield (Chapter 4)
Lecture 5: Thermal oxidation of Si (Chapter 6)
Lecture 6: Chemical Vapour Deposition and Physical Vapour Deposition (Chapter 10)
Lecture 7: Lithography 1 (Chapter 5.1 - 5.6)
Lecture 8: Wet etching and plasma etching (Chapter 9.1 - 9.10)
Lecture 9: Diffusion and doping (Chapter 7)
     Home Assignment 1
Lecture 10: Ion Implantation and Rapid Thermal Annealing (Chapter 8)
Lecture 11: Lithography (Chapter 5.7-5.8) and DWL, Lab1 and Lab2 presentations
Lecture 12: Interconnect technologies (Chapter 11) and Chemical Mechanical Planarization (Chapter 9.11)
Lecture 13: ALD (10.2.7) and ALE (9.10), Lab3 and Lab4 presentation
     Home Assignment 2
Lecture 14: Process Integration, Guest Lecture
Lecture 15: Process Integration, Lab5 and Lab 6 presentation
Lecture 16: Written exam
Lecture 17: Summary and Future technologies

 

Preparations before course start

Recommended prerequisites

Courses on BSc level or higher in solid-state physics and semiconductor devices.

Literature


Integrated Circuit Fabrication, James D. Plummer and Peter B. Griffin, Cambridge University Press, ISBN 978-1-009-30358-3

Examination and completion

Grading scale

A, B, C, D, E, FX, F

Examination

  • LAB1 - Lab, 1.0 credits, Grading scale: P, F
  • TENM - Oral exam, 4.0 credits, Grading scale: A, B, C, D, E, FX, F
  • TENS - Written exam, 2.5 credits, Grading scale: A, B, C, D, E, FX, F

Based on recommendation from KTH’s coordinator for disabilities, the examiner will decide how to adapt an examination for students with documented disability.

The examiner may apply another examination format when re-examining individual students.

Grading criteria/assessment criteria

The oral examination is conducted at Electrumbuilding, Level 3, room Commodore and 2 students participate in an examination slot of 60 min.
Students answer 7 questions each that are selected by Professor Mikael Östling.
Each question should be answered within 4 minutes (4x7=28 min).
Each question can give a maximum of 3 points.
As a general guide, it is required by the student to connect his/her answer to other areas covered in the course through a discussion with the examiner to acquire the highest 3 points on a specific question.
The grade on the oral examiantion will be based on the summation of the points achieved by the student on each question. The points for a specific grade will be as follow:
A = 20-21 points B = 17-19 points C = 13-16 points D = 11-12 points E = 9-10 points F < 9 points

The written examination is 2h long and consist of 6 questions. Each question can give maximum 4 points.
The grade on the written examiantion will be based on the summation of the points achieved by the student on each question. The points for a specific grade will be as follow:
A = 22-24 points B = 19-21 points C = 15-18 points D = 12-14 points E = 9-11 points F < 9 points

The grade on the course will be a weighted summation from the written and oral examination.

Ethical approach

  • All members of a group are responsible for the group's work.
  • In any assessment, every student shall honestly disclose any help received and sources used.
  • In an oral assessment, every student shall be able to present and answer questions about the entire assignment and solution.

Further information

No information inserted

Round Facts

Start date

Missing mandatory information

Course offering

  • Autumn 2024-10130
  • Autumn 2024-50772

Language Of Instruction

English

Offered By

EECS/Electrical Engineering

Contacts