Publications by Dimitrios Stathis
Peer reviewed
Articles
[1]
J. Xu et al., "Modeling Cycle-to-Cycle Variation in Memristors for In-Situ Unsupervised Trace-STDP Learning," IEEE Transactions on Circuits and Systems - II - Express Briefs, vol. 71, no. 2, pp. 627-631, 2024.
[2]
D. Wang et al., "A Memristor-Based Learning Engine for Synaptic Trace-Based Online Learning," IEEE Transactions on Biomedical Circuits and Systems, vol. 17, no. 5, pp. 1153-1165, 2023.
[3]
D. Stathis et al., "Clock tree generation by abutment in synchoros VLSI design," Microprocessors and microsystems, vol. 102, 2023.
[4]
N. M. Rezk et al., "MOHAQ : Multi-Objective Hardware-Aware Quantization of recurrent neural networks," Journal of systems architecture, vol. 133, 2022.
[5]
D. Pudi et al., "Methodology for Structured Data-Path Implementation in VLSI Physical Design : A Case Study," Electronics, vol. 11, no. 18, 2022.
[6]
D. Wang et al., "Mapping the BCPNN Learning Rule to a Memristor Model," Frontiers in Neuroscience, vol. 15, 2021.
[7]
Y. Yang et al., "Optimizing BCPNN Learning Rule for Memory Access," Frontiers in Neuroscience, vol. 14, 2020.
[8]
D. Stathis et al., "eBrainII : a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex," Journal of Signal Processing Systems, vol. 92, no. 11, pp. 1323-1343, 2020.
Conference papers
[9]
D. Wang et al., "FPGA-Based HPC for Associative Memory System," in 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024, 2024, pp. 52-57.
[10]
R. Kallapu et al., "DRRA-based Reconfigurable Architecture for Mixed-Radix FFT," in Proceedings of the IEEE International Conference on VLSI Design, 2023, pp. 25-30.
[11]
S. A. Mirsalari et al., "Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms," in ICECS 2023 - 2023 30th IEEE International Conference on Electronics, Circuits and Systems: Technosapiens for Saving Humanity, 2023.
[12]
J. Xu et al., "Optoelectronic memristor model for optical synaptic circuit of spiking neural networks," in 21st IEEE Interregional NEWCAS Conference, NEWCAS 2023 : Proceedings, 2023.
[13]
Y. Yang, D. Stathis and A. Hemani, "Reducing the Configuration Overhead of the Distributed Two-level Control System," in PROCEEDINGS OF THE 2022 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2022), 2022, pp. 104-107.
[14]
J. Xu et al., "A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation," in 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS, 2021.
[15]
D. Stathis et al., "Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortex," in PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021), 2021, pp. 685-688.
[16]
D. Stathis et al., "Clock Tree Generation by Abutment in Synchoros VLSI Design," in 2021 IEEE Nordic Circuits and Systems Conference (NorCAS), 2021, pp. 1-7.
[17]
A. K. Patan et al., "Design and Implementation of Optimized Register File for Streaming Applications," in 2021 25th International Symposium on VLSI Design and Test, VDAT 2021, 2021.
[18]
U. Altayo Gonzalez, D. Stathis and A. Hemani, "Synthesis of Predictable Global NoC by Abutment in Synchoros VLSI Design," in Proceedings - 2021 15th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2021, 2021, pp. 61-66.
[19]
V. Ntinas et al., "Cellular automata coupled with memristor devices : A fine unconventional computing paradigm," in 2020 International Conference on Electronics, Information, and Communication, ICEIC 2020, 2020.
[20]
G. Baccelli et al., "NACU : A Non-Linear Arithmetic Unit for Neural Networks," in PROCEEDINGS OF THE 2020 57TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2020.
[21]
D. Stathis et al., "Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps," in 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019, pp. 560-567.
[22]
P. Chaourani et al., "A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors," in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018.
[23]
J. Syed, A. Hemani and D. Stathis, "Can a reconfigurable architecture beat ASIC as a CNN accelerator?," in Proceedings - 2017 17th International Conference on Embedded Computer Systems : Architectures, Modeling, and Simulation, SAMOS 2017, 2018, pp. 97-104.
[24]
Y. Yang et al., "RiBoSOM : Rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform," in ACM International Conference Proceeding Series, 2018, pp. 105-114.
[25]
Y. Yang et al., "MTP-caffe : Memory, timing, and power aware tool for mapping CNNs to GPUs," in ACM International Conference Proceeding Series, 2017, pp. 31-36.
Non-peer reviewed
Theses
[26]
D. Stathis, "Synchoros VLSI Design Style," Doctoral thesis Stockholm : KTH Royal Institute of Technology, TRITA-EECS-AVL, 2022:30, 2022.
Reports
Other
[28]
Latest sync with DiVA:
2024-07-17 11:04:30