Publications by Per-Erik Hellström

Peer reviewed

Articles

[1]

D. Ramos Santesmases et al., "Simulation and Characterization of the Modulation Transfer Function in Fully Delineated Type-II Superlattices Infrared Detectors," IEEE Transactions on Electron Devices, vol. 71, no. 4, pp. 2459-2464, 2024.

[2]

D. Ramos Santesmases et al., "Optical concentration in fully delineated mid-wave infrared T2SL detectors arrays," Applied Physics Letters, vol. 123, no. 18, 2023.

[3]

D. Ramos Santesmases et al., "Two-step etch in n-on-p type-II superlattices for surface leakage reduction in mid-wave infrared megapixel detectors," Opto-Electronics Review, vol. 31, no. 1, 2023.

[4]

D. Ramos Santesmases et al., "Quasi-3-dimensional simulations and experimental validation of surface leakage currents in high operating temperature type-II superlattice infrared detectors," Journal of Applied Physics, vol. 132, no. 20, pp. 204501, 2022.

[5]

D. Ramos Santesmases et al., "1/f Noise and Dark Current Correlation in Midwave InAs/GaSb Type-II Superlattice IR Detectors," Physica Status Solidi (a) applications and materials science, vol. 218, no. 3, pp. 2000557, 2021.

[6]

S. Hou et al., "A Silicon Carbide 256 Pixel UV Image Sensor Array Operating at 400 degrees C," IEEE Journal of the Electron Devices Society, vol. 8, no. 1, pp. 116-121, 2020.

[7]

M. Vallejo-Perez et al., "Optimization of GOPS-Based Functionalization Process and Impact of Aptamer Grafting on the Si Nanonet FET Electrical Properties as First Steps towards Thrombin Electrical Detection," Nanomaterials, vol. 10, no. 9, 2020.

[8]

L. Zurauskaite, P.-E. Hellström and M. Östling, "Process Conditions for Low Interface State Density in Si-passivated Ge Devices with TmSiO Interfacial Layer," ECS Journal of Solid State Science and Technology, vol. 9, no. 12, 2020.

[9]

K. Garidis et al., "Selective epitaxial growth of in situ doped SiGe on bulk Ge for p+/n junction formation," Electronics, vol. 9, no. 4, 2020.

[10]

S. Hou et al., "A 4H-SiC BJT as a Switch for On-Chip Integrated UV Photodiode," IEEE Electron Device Letters, vol. 40, no. 1, pp. 51-54, 2019.

[11]

P. Chaourani et al., "Inductors in a Monolithic 3-D Process : Performance Analysis and Design Guidelines," IEEE Transactions on Very Large Scale Integration (vlsi) Systems, vol. 27, no. 2, pp. 468-480, 2019.

[12]

G. Jayakumar, P.-E. Hellström and M. Östling, "Utilizing the superior etch stop quality of HfO 2 in the front end of line wafer scale integration of silicon nanowire biosensors," Microelectronic Engineering, vol. 212, pp. 13-20, 2019.

[13]

G. Jayakumar et al., "Wafer-scale HfO 2 encapsulated silicon nanowire field effect transistor for efficient label-free DNA hybridization detection in dry environment," Nanotechnology, vol. 30, no. 18, 2019.

[14]

A. Abedin et al., "Germanium on Insulator Fabrication for Monolithic 3-D Integration," IEEE Journal of the Electron Devices Society, vol. 6, no. 1, pp. 588-593, 2018.

[15]

G. Jayakumar, P.-E. Hellström and M. Östling, "Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application," Micromachines, vol. 9, no. 11, 2018.

[16]

S. Hou et al., "Scaling and modeling of high temperature 4H-SiC p-i-n photodiodes," IEEE Journal of the Electron Devices Society, vol. 6, no. 1, pp. 139-145, 2018.

[17]

L. Jablonka et al., "Formation of nickel germanides from Ni layers with thickness below 10 nm," Journal of Vacuum Science & Technology B, vol. 35, no. 2, 2017.

[18]

S. Hou et al., "550 degrees C 4H-SiC p-i-n Photodiode Array With Two-Layer Metallization," IEEE Electron Device Letters, vol. 37, no. 12, pp. 1594-1596, 2016.

[19]

I. Z. Mitrovic et al., "Atomic-layer deposited thulium oxide as a passivation layer on germanium," Journal of Applied Physics, vol. 117, no. 21, 2015.

[20]

E. Dentoni Litta, P.-E. Hellström and M. Östling, "Enhanced channel mobility at sub-nm EOT by integration of a TmSiO interfacial layer in HfO2/TiN high-k/metal gate MOSFETs," IEEE Journal of the Electron Devices Society, vol. 3, no. 5, pp. 397-404, 2015.

[21]

E. D. Litta, P.-E. Hellström and M. Östling, "Integration of TmSiO/HfO2 Dielectric Stack in Sub-nm EOT High-k/Metal Gate CMOS Technology," IEEE Transactions on Electron Devices, vol. 62, no. 3, pp. 934-939, 2015.

[22]

M. Olyaei et al., "Low-frequency noise characterization in ultra-low equivalent-oxide-thickness thulium silicate interfacial layer nMOSFETs," IEEE Electron Device Letters, vol. 36, no. 12, pp. 1355-1358, 2015.

[23]

E. Dentoni Litta, P.-E. Hellström and M. Östling, "Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs," Solid-State Electronics, vol. 108, pp. 24-29, 2015.

[24]

E. Dentoni Litta et al., "Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology," Solid-State Electronics, vol. 98, pp. 20-25, 2014.

[25]

G. Jayakumar et al., "Fabrication and characterization of silicon nanowires using STL for biosensing applications," INT CONF ULTI INTEGR, pp. 109-112, 2014.

[26]

G. Jayakumar et al., "Silicon nanowires integrated with CMOS circuits for biosensing application," Solid-State Electronics, vol. 98, pp. 26-31, 2014.

[27]

E. Dentoni Litta et al., "High-Deposition-Rate Atomic Layer Deposition of Thulium Oxide from TmCp3 and H2O," Journal of the Electrochemical Society, vol. 160, no. 11, pp. D538-D542, 2013.

[28]

I. Z. Mitrovic et al., "Interface engineering of Ge using thulium oxide : Band line-up study," Microelectronic Engineering, vol. 109, pp. 204-207, 2013.

[29]

V. Gudmundsson et al., "Simulation of low Schottky barrier MOSFETs using an improved Multi-subband Monte Carlo model," Solid-State Electronics, vol. 79, pp. 172-178, 2013.

[30]

E. Dentoni Litta et al., "Thulium silicate interfacial layer for scalable high-k/metal gate stacks," IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3271-3276, 2013.

[31]

V. Gudmundsson, P.-E. Hellström and M. Östling, "Error Propagation in Contact Resistivity Extraction Using Cross-Bridge Kelvin Resistors," IEEE Transactions on Electron Devices, vol. 59, no. 6, pp. 1585-1591, 2012.

[32]

C. Henkel et al., "Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks," Solid-State Electronics, vol. 74, pp. 7-12, 2012.

[33]

M. Olyaei et al., "Low-Frequency Noise in High-k LaLuO₃/TiN MOSFETs," Solid-State Electronics, vol. 78, no. SI, pp. 51-55, 2012.

[34]

L. Donetti et al., "Hole effective mass in silicon inversion layers with different substrate orientations and channel directions," Journal of Applied Physics, vol. 110, no. 6, pp. 063711, 2011.

[35]

S. M. Thomas et al., "On the role of Coulomb scattering in hafnium-silicate gated silicon n and p-channel metal-oxide-semiconductor-field-effect-transistors," Journal of Applied Physics, vol. 110, no. 12, pp. 124503, 2011.

[36]

S. Persson et al., "Strained-Silicon Heterojunction Bipolar Transistor," IEEE Transactions on Electron Devices, vol. 57, no. 6, pp. 1243-1252, 2010.

[37]

J. Luo et al., "Effect of carbon on Schottky barrier heights of NiSi modified by dopant segregation," IEEE Electron Device Letters, vol. 30, no. 6, 2009.

[38]

J. Luo et al., "Effects of Carbon on Schottky Barrier Heights of NiSi Modified by Dopant Segregation," IEEE Electron Device Letters, vol. 30, no. 6, pp. 608-610, 2009.

[39]

V. Gudmundsson et al., "Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation," IEEE Electron Device Letters, vol. 30, no. 5, pp. 541-543, 2009.

[40]

S. H. Olsen et al., "Strained Si/SiGe MOS technology : Improving gate dielectric integrity," Microelectronic Engineering, vol. 86, no. 3, pp. 218-223, 2009.

[41]

F. Driussi et al., "On the electron mobility enhancement in biaxially strained Si MOSFETs," Solid-State Electronics, vol. 52, no. 4, pp. 498-505, 2008.

[42]

Z. Zhang et al., "Performance fluctuation of FinFETs with Schottky barrier source/drain," IEEE Electron Device Letters, vol. 29, no. 5, pp. 506-508, 2008.

[43]

A. O'Neill et al., "Reduced self-heating by strained silicon substrate engineering," Applied Surface Science, vol. 254, no. 19, pp. 6182-6185, 2008.

[44]

Z. Zhang et al., "SB-MOSFETs in UTB-SOI featuring PtSi source/drain with dopant segregation," IEEE Electron Device Letters, vol. 29, no. 1, pp. 125-127, 2008.

[45]

J. Hållstedt, P.-E. Hellström and H. H. Radamson, "Sidewall transfer lithography for reliable fabrication of nanowires and deca-nanometer MOSFETs," Thin Solid Films, vol. 517, no. 1, pp. 117-120, 2008.

[46]

M. von Haartman et al., "Impact of strain and channel orientation on the low-frequency noise performance of Si n- and pMOSFETs," Solid-State Electronics, vol. 51, no. 5, pp. 771-777, 2007.

[47]

Z. Zhang et al., "A novel self-aligned process for platinum silicide nanowires," Microelectronic Engineering, vol. 83, no. 11-12, pp. 2107-2111, 2006.

[48]

J. Hållstedt et al., "A robust spacer gate process for deca-nanometer high-frequency MOSFETs," Microelectronic Engineering, vol. 83, no. 3, pp. 434-439, 2006.

[49]

S. H. Olsen et al., "Control of self-heating in thin virtual substrate strained Si MOSFETs," IEEE Transactions on Electron Devices, vol. 53, no. 9, pp. 2296-2305, 2006.

[50]

Z. Zhang et al., "Electrically robust ultralong nanowires of NiSi, Ni2Si and Ni31Si12," Applied Physics Letters, vol. 88, no. 4, pp. 043104, 2006.

[51]

J. Hållstedt et al., "Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels," IEEE Electron Device Letters, vol. 27, no. 6, pp. 466-468, 2006.

[52]

Z. Zhang et al., "Ni2Si nanowires of extraordinarily low resistivity," Applied Physics Letters, vol. 88, no. 21, pp. 213103, 2006.

[53]

J. Hållstedt et al., "Noise and mobility characteristics of bulk and fully depleted SOI pMOSFETs using Si or SiGe channels," ECS Transactions, vol. 3, no. 7, pp. 67-72, 2006.

[54]

J. B. Varzgar et al., "Reliability study of ultra-thin gate oxides on strained-Si/SiGe MOS structures," Materials Science & Engineering : B. Solid-state Materials for Advanced Technology, vol. 135, no. 3, pp. 203-206, 2006.

[55]

J. Seger et al., "Lateral encroachment of Ni-silicides in the source/drain regions on ultrathin silicon-on-insulator," Applied Physics Letters, vol. 86, no. 25, 2005.

[56]

M. von Haartman et al., "Low-frequency noise and Coulomb scattering in Si0.8Ge0.2 surface channel pMOSFETs with ALD Al2O3 gate dielectrics," Solid-State Electronics, vol. 49, no. 6, pp. 907-914, 2005.

[57]

D. Wu et al., "Ni-salicided CMOS with a poly-SiGe/Al2O3/HfO2/Al2O3 gate stack," Microelectronic Engineering, vol. 77, no. 1, pp. 36-41, 2005.

[58]

C. Isheden et al., "pMOSFETs with recessed and selectively regrown Si1-xGex source/drain junctions," Materials Science in Semiconductor Processing, vol. 8, no. 1-3, pp. 359-362, 2005.

[59]

C. Isheden et al., "Formation of shallow junctions by HCl-based Si etch followed by selective epitaxy of B-doped Si1-xGex in RPCVD," Journal of the Electrochemical Society, vol. 151, no. 6, pp. C365-C368, 2004.

[60]

D. Wu et al., "Influence of surface treatment prior to ALD high-kappa dielectrics on the performance of SiGe surface-channel pMOSFETs," IEEE Electron Device Letters, vol. 25, no. 5, pp. 289-291, 2004.

[61]

M. von Haartman et al., "Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics," Solid-State Electronics, vol. 48, no. 12, pp. 2271-2275, 2004.

[62]

C. Isheden et al., "MOSFETs with recessed SiGe Source/Drain junctions formed by selective etching and growth," Electrochemical and solid-state letters, vol. 7, no. 4, pp. G53-G55, 2004.

[63]

J. Hållstedt et al., "Methods to reduce the loading effect in selective and non-selective epitaxial growth of sigec layers," Materials Science & Engineering : B. Solid-state Materials for Advanced Technology, vol. 109, no. 03-jan, pp. 122-126, 2004.

[64]

D. Wu et al., "Notched-gate pMOSFET with ALD TiN/high-kappa gate stack formed by selective wet etching," Electrochemical and solid-state letters, vol. 7, no. 10, pp. G228-G230, 2004.

[65]

S. Persson et al., "Quantifying hole mobility degradation in pMOSFETs with a strained-Si0.7Ge0.3 surface-channel under an ALD TiN/Al2O3/HfAlOx/Al2O3 gate stack," Solid-State Electronics, vol. 48, no. 5, pp. 721-729, 2004.

[66]

C. Isheden et al., "Selective Si etching using HCl vapor," Physica Scripta, vol. T114, pp. 107-109, 2004.

[67]

S. Persson et al., "Variation of contact resistivity with Ge in TiW/p(+) SiGe contacts," Physica Scripta, vol. T114, pp. 49-52, 2004.

[68]

M. von Haartman et al., "1/f noise in Si and Si0.7Ge0.3 pMOSFETs," IEEE Transactions on Electron Devices, vol. 50, pp. 2513-2519, 2003.

[69]

D. Wu et al., "A novel strained Si0.7Ge0.3 surface-channel pMOSFET with an ALD TiN/Al2O3/HfAlOx/Al2O3 gate stack," IEEE Electron Device Letters, vol. 24, no. 3, pp. 171-173, 2003.

[70]

S. Persson, P.-E. Hellberg and S.-L. Zhang, "A charge sheet model for MOSFETs with an abrupt retrograde channel - Part I. Drain current and body charge," Solid-State Electronics, vol. 46, no. 12, pp. 2209-2216, 2002.

[71]

S. Persson, P.-E. Hellberg and S.-L. Zhang, "A charge sheet model for MOSFETs with an abrupt retrograde channel - Part II. Charges and intrinsic capacitances," Solid-State Electronics, vol. 46, no. 12, pp. 2217-2225, 2002.

[72]

J. Åberg et al., "Electrical properties of the TiSi2-Si transition region in contacts : The influence of an interposed layer of Nb," Journal of Applied Physics, vol. 90, pp. 2380-2388, 2001.

[73]

J. Aberg et al., "Electrical properties of the TiSi2-Si transition region in contacts : The influence of an interposed layer of Nb," Journal of Applied Physics, vol. 90, no. 5, pp. 2380-2388, 2001.

[74]

P.-E. Hellberg et al., "Threshold voltage control for PMOSFETs using an undoped epitaxial Si channel and a p(+)-SixGe1-x gate," Solid-State Electronics, vol. 44, no. 11, pp. 2085-2088, 2000.

[75]

P.-E. Hellberg et al., "Threshold voltage control for PMOSFETs using an undoped epitaxial Si channel and a p+-SixGe1-x gate," Solid-State Electronics, vol. 44, pp. 2085-2088, 2000.

[76]

J. Grahn, P.-E. Hellberg and E. Olsson, "Effect of growth temperature on the properties of evaporated tantalum pentoxide thin films on silicon deposited using oxygen radicals," Journal of Applied Physics, vol. 84, pp. 1632-1642, 1998.

[77]

P.-E. Hellberg et al., "Boron-doped polycrystalline SixGe1-x films : Dopant activation and solid solubility," Journal of the Electrochemical Society, vol. 144, pp. 3968-3973, 1997.

[78]

P.-E. Hellberg et al., "Oxidation of silicon-germanium alloys. I. An experimental study," Journal of Applied Physics, vol. 82, pp. 5773-5778, 1997.

[79]

P.-E. Hellberg et al., "Oxidation of silicon-germanium alloys. II. A mathematical model," Journal of Applied Physics, vol. 82, pp. 5779-5787, 1997.

[80]

P.-E. Hellberg, S.-L. Zhang and C. Petersson, "Work function of Boron-Doped polycrystalline SixGe1-x films," IEEE Electron Device Letters, vol. 18, pp. 456-458, 1997.

[81]

J. Hudner et al., "Tantalum oxide films on silicon grown by tantalum evaporation in atomic oxygen," Thin Solid Films, vol. 281-282, pp. 415-418, 1996.

Conference papers

[82]

L. Zurauskaite, M. Östling and P.-E. Hellström, "Improvement on Ge/GeOx/Tm2O3/HfO2 Gate Performance by Forming Gas Anneal," in IEEE 51st European Solid-State Device Research Conference ESSDERC 2021, Grenoble, France [virtual] 13-17 September 2021, 2021.

[83]

L. Zurauskaite, M. Östling and P.-E. Hellström, "Improvement on Ge/GeOx/Tm2O3/HfO2 Gate Performance by Forming Gas Anneal," in IEEE 51ST EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2021), 2021, pp. 227-230.

[84]

M. Ekström, L. Zurauskaite and P.-E. Hellström, "Si thickness influence on subthreshold currents at high temperatures in FDSOI CMOS," in 2021 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (EUROSOI-ULIS), 2021.

[85]

L. Zurauskaite et al., "Si-passivated Ge Gate stacks with low interface state and oxide trap densities using thulium silicate," in ECS Transactions, 2020, pp. 387-393.

[86]

S. Hou et al., "High Temperature High Current Gain IC Compatible 4H-SiC Phototransistor," in European Conference on Silicon Carbide and Related Materials (ECSCRM 2018), Birmingham, United Kingdom, 2-6 September 2018, 2019.

[87]

S. Hou et al., "Process Control and Optimization of 4H-SiC Semiconductor Devices and Circuits," in Proceedings of the 3rd Electron Devices Technology and Manufacturing, (EDTM) Conference 2019, 2019.

[88]

P. Chaourani et al., "A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors," in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018.

[89]

A. Abedin et al., "GOI fabrication for monolithic 3D integration," in 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, 2018, pp. 1-3.

[90]

L. Zurauskaite et al., "Investigation of Tm₂O₃ as a gate dielectric for Ge MOS devices," in ECS Transactions, 2018, pp. 67-73.

[91]

S. Hou et al., "4H-SiC PIN diode as high temperature multifunction sensor," in 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016, 2017, pp. 630-633.

[92]

P. Chaourani et al., "Enabling Area Efficient RF ICs through Monolithic 3D Integration," in Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, 2017, pp. 610-613.

[93]

S. Hou et al., "Scaling of 4H-SiC p-i-n photodiodes for high temperature applications," in 2017 75th Annual Device Research Conference (DRC), 2017.

[94]

L. Zurauskaite, P.-E. Hellström and M. Östling, "The impact of atomic layer depositions on high quality Ge/GeO2 interfaces fabricated by rapid thermal annealing in O2 ambient," in 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings, 2017, pp. 164-166.

[95]

E. Dentoni Litta, P.-E. Hellström and M. Östling, "(Invited) TmSiO As a CMOS-Compatible High-k Dielectric," in SILICON COMPATIBLE MATERIALS, PROCESSES, AND TECHNOLOGIES FOR ADVANCED INTEGRATED CIRCUITS AND EMERGING APPLICATIONS 6, 2016, pp. 79-89.

[96]

A. Abedin et al., "Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density," in ECS Transactions, 2016, pp. 615-621.

[97]

G. Jayakumar et al., "Fabrication and characterization of high-K dielectric integrated silicon nanowire sensor for DNA sensing application," in BIOSENSING AND NANOMEDICINE IX, 2016.

[98]

K. Garidis et al., "Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration," in EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015, pp. 165-168.

[99]

E. Dentoni Litta, P.-E. Hellström and M. Östling, "Effective Workfunction Control in TmSiO/HfO2 high-k/metal gate stacks," in ULIS 2014 : 2014 15th International Conference on Ultimate Integration on Silicon, 2014, pp. 69-72.

[100]

A. Asadollahi et al., "Fabrication of relaxed germanium on insulator via room temperature wafer bonding," in ECS Transactions : Volume 64, Cancun, Mexico, October 5 – 9, 2014 2014 ECS and SMEQ Joint International Meeting, 2014, pp. 533-541.

[101]

A. Asadollahi et al., "Fabrication of strained Ge on insulator via room temperature wafer bonding," in 2014 15th International Conference on Ultimate Integration on Silicon, ULIS 2014, 2014, pp. 81-84.

[102]

M. Olyaei et al., "Improved Low-frequency Noise for 0.3nm EOT Thulium Silicate Interfacial Layer," in Solid State Device Research Conference (ESSDERC), 2014 44th European, 2014, pp. 361-364.

[103]

I. Z. Mitrovic et al., "Interface engineering routes for a future cmos ge-based technology," in ECS Transactions, 2014, pp. 73-88.

[104]

P.-E. Hellström, E. Dentoni Litta and M. Östling, "Interfacial layer engineering using thulium silicate/germanate for high-k/metal gate MOSFETs," in ECS Transactions : Cancun, Mexico, October 5 – 9, 2014 2014 ECS and SMEQ Joint International Meeting, 2014, pp. 249-260.

[105]

M. Östling, E. Dentoni Litta and P.-E. Hellström, "Recent advances in high-k dielectrics and inter layer engineering," in Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014, 2014.

[106]

M. Olyaei et al., "A study of low-frequency noise on high-k/metal gate stacks with in situ SiOx interfacial layer," in 2013 22nd International Conference on Noise and Fluctuations, ICNF 2013, 2013, pp. 1-4.

[107]

E. Dentoni Litta et al., "Characterization of thulium silicate interfacial layer for high-k/metal gate MOSFETs," in 2013 14th International Conference On Ultimate Integration On Silicon (ULIS), 2013, pp. 122-125.

[108]

E. Dentoni Litta, P.-E. Hellström and M. Östling, "Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs," in 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2013, pp. 155-158.

[109]

G. Jayakumar et al., "Silicon Nanowires Integrated in a Fully Depleted CMOS Process for Charge Based Biosensing," in ULIS 2013 : The 14th International Conference on Ultimate Integration on Silicon, Incorporating the 'Technology Briefing Day', 2013, pp. 81-84.

[110]

M. Östling et al., "Atomic layer deposition-based interface engineering for high-k/metal gate stacks," in ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2012, p. 6467643.

[111]

E. Dentoni Litta et al., "In situ SiOx interfacial layer formation for scaled ALD high-k/metal gate stacks," in 2012 13th International Conference on Ultimate Integration on Silicon, ULIS 2012, 2012, pp. 105-108.

[112]

V. Gudmundsson, P.-E. Hellström and M. Östling, "Effect of Be segregation on NiSi/Si Schottky barrier heights," in Solid-State Device Research Conference (ESSDERC), 2011.

[113]

C. Henkel et al., "Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks," in European Solid-State Device Res. Conf., 2011, pp. 75-78.

[114]

M. Olyaei et al., "Low-frequency Noise in High-k LaLuO₃/TiN MOSFETs," in 2011 International Semiconductor Device Research Symposium (ISDRS), 2011, pp. TA01-TA04.

[115]

L. Donetti et al., "On the effective mass of holes in inversion layers," in International Conference on Ultimate Integration on Silicon, 2011, pp. 50-53.

[116]

M. Östling et al., "Technology challenges in silicon devices beyond the 16 nm node," in Proceedings of the 18th International Conference : Mixed Design of Integrated Circuits and Systems, MIXDES 2011, 2011, pp. 27-31.

[117]

M. Östling et al., "Integration of metallic source/drain (MSD) contacts in nanoscaled CMOS technology," in ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2010, pp. 41-45.

[118]

V. Gudmundsson et al., "Multi-subband Monte Carlo simulation of fully-depleted silicon-on-insulator Schottky barrier MOSFETs," in 11th International Conference on Ultimate Integration of Silicon (ULIS), 2010, 2010.

[119]

M. Östling et al., "Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts," in 2010 27th International Conference on Microelectronics, MIEL 2010 - Proceedings, 2010, pp. 9-13.

[120]

V. Gudmundsson et al., "Characterization of dopant segregated Schottky barrier source/drain contacts," in ULIS 2009 : 10TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION OF SILICON, 2009, pp. 73-76.

[121]

V. Gudmundsson et al., "Direct measurement of sidewall roughness on Si, poly-Si and poly-SiGe by AFM," in PROCEEDINGS OF THE 17TH INTERNATIONAL VACUUM CONGRESS/13TH INTERNATIONAL CONFERENCE ON SURFACE SCIENCE/INTERNATIONAL CONFERENCE ON NANOSCIENCE AND TECHNOLOGY, 2008.

[122]

S. Persson et al., "Fabrication and characterisation of strained Si heterojunction bipolar transistors on virtual substrates," in IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST, 2008, pp. 735-738.

[123]

B. G. Malm et al., "Noise Properties of High-Mobility, 80 nm Gate Length MOSFETs on Supercritical Virtual Substrates," in SIGE, GE, AND RELATED COMPOUNDS 3: MATERIALS, PROCESSING, AND DEVICES : MATERIALS, PROCESSING, AND DEVICES, 2008, pp. 529-537.

[124]

Z. Qiu et al., "Role of Si implantation in control of underlap length in Schottky-barrier source/drain MOSFETs on ultrathin body SOI," in ULIS 2008 : PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON, 2008, pp. 175-178.

[125]

M. Östling et al., "Towards Schottky-Barrier Source/Drain MOSFETs," in 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, pp. 146-149.

[126]

M. Östling et al., "Critical technology issues for deca-nanometer MOSFETs," in ICSICT-2006 : 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2007, pp. 27-30.

[127]

J. Hållstedt et al., "Leakage current reduction in 80 nm biaxially strained Si nMOSFETs on in-situ doped SiGe virtual substrates," in ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference 2008, 2007, pp. 319-322.

[128]

A. O'Neill et al., "Strained silicon technology," in ICSICT-2006 : 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2007, pp. 104-107.

[129]

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P.-E. Hellström et al., "Strained-Si NMOSFETs on thin 200 nm virtual substrates," in 2005 International Semiconductor Device Research Symposium; Bethesda, MD; United States; 7 December 2005 through 9 December 2005, 2005, pp. 185-186.

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Non-peer reviewed

Chapters in books

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M. Östling, E. Dentoni Litta and P.-E. Hellström, "Three-Dimensional Integration of Ge and Two-Dimensional Materials for One-Dimensional Devices," in Future Trends in Microelectronics: Journey into the Unknown, : wiley, 2016, pp. 51-67.

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J. Bolten et al., "Fabrication of Nanowires," in Beyond CMOS Nanodevices 1, : Wiley Blackwell, 2014, pp. 5-23.

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P.-E. Hellström, G. Jayakumar and M. Östling, "Integration of Silicon Nanowires with CMOS," in Beyond CMOS Nanodevices 1, : Wiley Blackwell, 2014, pp. 65-72.