Publications by Ingo Sander
Peer reviewed
Articles
[1]
R. Jordao, M. Becker and I. Sander, "IDeSyDe : Systematic Design Space Exploration via Design Space Identification," ACM Transactions on Design Automation of Electronic Systems, vol. 29, no. 5, 2024.
[2]
C. Schwartz et al., "Satellite Image Compression Guided by Regions of Interest," Sensors, vol. 23, no. 2, 2023.
[3]
S. -. Attarzadeh-Niaki, I. Sander and M. Ahmadi, "An automated parallel simulation flow for cyber-physical system design," Integration, vol. 77, pp. 48-58, 2021.
[4]
D. S. Loubach et al., "Classification and Mapping of Model Elements for Designing Runtime Reconfigurable Systems," IEEE Access, vol. 9, pp. 156337-156360, 2021.
[5]
G. Ungureanu et al., "ForSyDe-Atom : Taming Complexity in Cyber Physical System Design with Layers," ACM Transactions on Embedded Computing Systems, vol. 20, no. 2, 2021.
[6]
S. -. Attarzadeh-Niaki and I. Sander, "Heterogeneous co-simulation for embedded and cyber-physical systems design," Simulation (San Diego, Calif.), vol. 96, no. 9, pp. 753-765, 2020.
[7]
R. Bonna et al., "Modeling and Simulation of Dynamic Applications Using Scenario-Aware Dataflow," ACM Transactions on Design Automation of Electronic Systems, vol. 24, no. 5, 2019.
[8]
K. Rosvall and I. Sander, "Flexible and Tradeoff-Aware Constraint-Based Design Space Exploration for Streaming Applications on Heterogeneous Platforms," ACM Transactions on Design Automation of Electronic Systems, vol. 23, no. 2, 2018.
[9]
K. Grüttner et al., "CONTREX : Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties," Microprocessors and microsystems, vol. 51, pp. 39-55, 2017.
[10]
M. Fakih et al., "SAFEPOWER project : Architecture for safe and power-efficient mixed-criticality systems," Microprocessors and microsystems, vol. 52, pp. 89-105, 2017.
[11]
S.-H. Attarzadeh-Niaki and I. Sander, "An extensible modeling methodology for embedded and cyber-physical system design," Simulation (San Diego, Calif.), vol. 92, no. 8, pp. 771-794, 2016.
[12]
J. Zhu, I. Sander and A. Jantsch, "Performance Analysis of Reconfigurations in Adaptive Real-Time Streaming Applications," ACM Transactions on Embedded Computing Systems, vol. 11, no. 1, 2012.
[13]
T. Raudvere, I. Sander and A. Jantsch, "Application and. verification of local nonsemantic-preserving transformations in system-design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 6, pp. 1091-1103, 2008.
[14]
I. Sander and A. Jantsch, "Modelling Adaptive Systems in ForSyDe," Electronic Notes in Theoretical Computer Science, vol. 200, no. 2, pp. 39-54, 2008.
[15]
A. Jantsch and I. Sander, "Models of computation and languages for embedded system design," IEE Proceedings - Computers and digital Techniques, vol. 152, no. 2, pp. 114-129, 2005.
[16]
I. Sander and A. Jantsch, "System modeling and transformational design refinement in ForSyDe," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 1, pp. 17-32, 2004.
[17]
I. Sander, A. Jantsch and Z. Lu, "Development and application of design transformations in ForSyDe," IEE Proceedings - Computers and digital Techniques, vol. 150, no. 5, pp. 313-320, 2003.
Conference papers
[18]
R. Chen and I. Sander, "A Quantitative Type Approach to Formal Component-Based System Design," in 2024 forum on specification & design languages, FDL 2024, 2024, pp. 27-36.
[19]
F. Bahrami et al., "Automatic Parallelization of Embedded Software via Hierarchical Process Network Transformations," in 2024 forum on specification & design languages, FDL 2024, 2024, pp. 37-45.
[20]
R. Jordao et al., "Multi-objective preference-free exact design space exploration of static DSP on multicore platforms," in 2024 forum on specification & design languages, FDL 2024, 2024, pp. 59-67.
[21]
R. Jordao et al., "Design space exploration for safe and optimal mapping of avionics functionality on IMA platforms," in AIAA/IEEE Digital Avionics Systems Conference : Proceedings, 2023.
[22]
R. Jordao et al., "A multi-view and programming language agnostic framework for model-driven engineering," in PROCEEDINGS OF THE 2022 FORUM ON SPECIFICATION & DESIGN LANGUAGES (FDL), 2022.
[23]
C. Schwartz et al., "On-board Satellite Data Processing to Achieve Smart Information Collection," in Proceedings of SPIE - The International Society for Optical Engineering, 2022.
[24]
I. Sander et al., "TOWARDS CORRECT-BY-CONSTRUCTION DESIGN OF SAFETY-CRITICAL EMBEDDED AVIONICS SYSTEMS," in 33rd Congress of the International Council of the Aeronautical Sciences, ICAS 2022, 2022, pp. 1637-1658.
[25]
R. Jordao, I. Sander and M. Becker, "Formulation of Design Space Exploration Problems by Composable Design Space Identification," in PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021), 2021, pp. 1204-1207.
[26]
G. Ungureanu, R. Jordao and I. Sander, "Exploiting Dataflow Models for Parallel Simulation of Discrete Timed Systems," in Proceedings of the 2020 Forum for Specification & Design Languages (FDL), 2020.
[27]
G. Ungureanu et al., "Formal design, co-simulation and validation of a radar signal processing system," in Proceedings of the 2019 Forum on Specification and Design Languages, FDL 2019, 2019.
[28]
Jose. E. G. de Medeiros, G. Ungureanu and I. Sander, "An Algebra for Modeling Continuous Time Systems," in PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2018, pp. 861-864.
[29]
G. Ungureanu, J. E. G. de Medeiros and I. Sander, "Bridging Discrete and Continuous Time Models with Atoms," in PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2018, pp. 277-280.
[30]
K. Rosvall et al., "Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors," in 2018 21st Euromicro Conference on Digital System Design (DSD), 2018.
[31]
G. Ungureanu and I. Sander, "A layered formal framework for modeling of cyber-physical systems," in Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, 2017, pp. 1715-1720.
[32]
S. -. Attarzadeh-Niaki and I. Sander, "Automatic construction of models for analytic system-level design space exploration problems," in Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, 2017, pp. 670-673.
[33]
K. Rosvall et al., "Throughput propagation in constraint-based design space exploration for mixed-criticality systems," in ACM International Conference Proceeding Series, 2017.
[34]
N. Khalilzad, K. Rosvall and I. Sander, "A modular design space exploration framework for multiprocessor real-time systems," in Forum on Specification and Design Languages, 2016.
[35]
R. Gorgen et al., "CONTREX : Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties," in 19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016), 2016, pp. 286-293.
[36]
A. Lenz et al., "SAFEPOWER project : Architecture for Safe and Power-Efficient Mixed-Criticality Systems," in 19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016), 2016, pp. 294-300.
[37]
G. Hjort Blindell, C. Menne and I. Sander, "Synthesizing Code for GPGPUs from abstract formal models," in 16th Conference on Languages, Design Methods, and Tools for Electronic System Design, FDL 2014, 2016, pp. 115-134.
[38]
S.-H. Attarzadeh-Niaki et al., "A Composable and Predictable MPSoC Design Flow for Multiple Real-Time Applications," in 1st Workshop on Model-Implementation Fidelity (MiFi), March 13, 2015, Grenoble,France, 2015.
[39]
P. I. Diallo et al., "A formal, model-driven design flow for system simulation and multi-core implementation," in 2015 10th IEEE International Symposium on Industrial Embedded Systems, 2015, pp. 254-263.
[40]
F. Herrera et al., "An efficient joint analytical and simulation-based design space exploration flow for predictable multi-core systems," in ACM International Conference Proceeding Series, 2015.
[41]
F. Herrera and I. Sander, "An extensible infrastructure for modeling and time analysis of predictable embedded systems," in Forum on Specification and Design Languages, 2015.
[42]
F. Herrera and I. Sander, "Combining analytical and simulation-based design space exploration for efficient time-critical and mixed-criticality systems," in Forum on Specification and Design Languages, FDL 2013, 2015, pp. 167-188.
[43]
E. Paone et al., "Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints," in Proceedings -Design, Automation and Test in Europe, DATE, 2015, pp. 736-741.
[44]
S. H. Attarzadeh-Niaki and I. Sander, "Integrating Functional Mock-up units into a formal heterogeneous system modeling framework," in 18th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2015, 2015.
[45]
B. Navas, I. Sander and J. Öberg, "Towards cognitive reconfigurable hardware : Self-aware learning in RTR fault-tolerant SoCs," in Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015, 2015.
[46]
K. Rosvall and I. Sander, "A constraint-based design space exploration framework for real-time applications on MPSoCs," in Proceedings -Design, Automation and Test in Europe, DATE 2014, 2014, pp. 1-6.
[47]
B. Navas, J. Öberg and I. Sander, "On providing scalable self-healing adaptive fault-tolerance to RTR SoCs," in Proceedings of ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on, 2014, pp. 1-6.
[48]
G. Hjort Blindell, C. Menne and I. Sander, "Synthesizing Code for GPGPUs from Abstract Formal Models," in Forum on specification and Design Languages (FDL), Munich, Germany, October 14-16, 2014, 2014.
[49]
B. Navas, J. Öberg and I. Sander, "The Upset-Fault-Observer : A Concept for Self-healing Adaptive Fault Tolerance," in Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2014, 2014, pp. 89-96.
[50]
S. H. Attarzadeh Niaki and I. Sander, "An Automated Parallel Simulation Flow for Heterogeneous Embedded Systems," in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013, pp. 27-30.
[51]
F. Herrera and I. Sander, "Combining Analytical and Simulation-based Design Space Exploration for Time-Critical Systems," in Forum on Specification & Design Languages (FDL), 2013, 2013, p. 6646657.
[52]
G. Ungureanu et al., "Parallel software design enabling high-speed reliability testing of inkjet printheads," in International Conference on Digital Printing Technologies, 2013, pp. 60-65.
[53]
S. H. Attarzadeh Niaki, M. Mikulcak and I. Sander, "Rapid virtual prototyping of real-time systems using predictable platform characterizations," in Forum on Specification Design Languages (FDL) 2013, 2013, p. 6646652.
[54]
S. Li et al., "System level synthesis of hardware for DSP applications using pre-characterized function implementations," in 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2013.
[55]
B. Navas, I. Sander and J. Öberg, "The RecoBlock SoC Platform : A Flexible Array of Reusable Run-Time-Reconfigurable IP-Blocks," in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013, pp. 833-838.
[56]
F. Herrera, H. Attarzadeh and I. Sander, "Towards a Modelling and Design Framework for Mixed-Criticality SoCs and Systems-of-Systems," in Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, 2013, pp. 989-996.
[57]
B. Navas, J. Öberg and I. Sander, "Towards the generic reconfigurable accelerator : Algorithm development, core design, and performance analysis," in 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013; Cancun; Mexico, 2013, pp. 1-6.
[58]
S. H. Attarzadeh Niaki et al., "Formal heterogeneous system modeling with SystemC," in Proceedings of Forum on Specification and Design Languages (FDL) 2012, 2012, pp. 160-167.
[59]
S. H. Attarzadeh Niaki et al., "Heterogeneous system-level modeling for small and medium enterprises," in Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium on, 2012, pp. 1-6.
[60]
G. S. Beserra, S. H. Attarzadeh Niaki and I. Sander, "Integrating virtual platforms into a heterogeneous MoC-based modeling framework," in Proceedings of Forum on Specification and Design Languages (FDL) 2012, 2012, pp. 143-150.
[61]
S. H. Attarzadeh Niaki and I. Sander, "Co-simulation of embedded systems in a heterogeneous MoC-based modeling framework," in 2011 6th IEEE International Symposium on Industrial Embedded Systems (SIES) : Proceedings of a meeting held 15-17 June 2011, Vasteras, Sweden., 2011, pp. 238-247.
[62]
S. H. Attarzadeh Niaki and I. Sander, "Semi-formal refinement of heterogeneous embedded systems by foreign model integration," in 2011 Forum on Specification and Design Languages (FDL), 2011, pp. 179-186.
[63]
M. K. Jakobsen et al., "System level modelling with open source tools," in Embedded World Conference 2011, 2011.
[64]
I. Sander and S. H. Attarzadeh Niaki, "Towards a Formal Software Synthesis Methodology for Embedded Multiprocessor Systems," in Proceedings of First International Software Technology Exchange Workshop 2011, 2011.
[65]
J. Zhu, I. Sander and A. Jantsch, "Constrained Global Scheduling of Streaming Applications on MPSoCs," in 2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, pp. 223-228.
[66]
J. Zhu, I. Sander and A. Jantsch, "HetMoC : Heterogeneous Modeling in SystemC," in Proceedings of the Forum on Design Langauges (FDL), 2010, pp. 117-122.
[67]
J. Zhu, I. Sander and A. Jantsch, "Pareto Efficient Design for Reconfigurable Streaming Applications on CPU/FPGAs," in Proceedings of Design Automation and Test in Europe (DATE ’10), 2010, pp. 1035-1040.
[68]
J. Zhu, I. Sander and A. Jantsch, "Buffer Minimization of Real-Time Streaming Applications Scheduling on Hybrid CPU/FPGA Architectures," in DATE : 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, 2009, pp. 1506-1511.
[69]
B. Navas, I. Sander and J. Öberg, "Camera and LCM IP-Cores for NIOS SOPC System," in 6th FPGAworld Conference, Academic Proceedings 2009, 2009, pp. 18-23.
[70]
W. H. Minhass, J. Öberg and I. Sander, "Design and implementation of a plesiochronous multi-core 4x4 network-on-chip FPGA platform with MPI HAL support," in 6th FPGAworld Conference, Academic Proceedings 2009, 2009, pp. 52-57.
[71]
I. Sander, A. Acosta and A. Jantsch, "Hardware Design and Synthesis in ForSyDe," in Proceedings of Hardware Design and Functional Languages, 2009.
[72]
I. Sander et al., "High-Level Estimation and Trade-Off Analysis for Adaptive Real-Time Systems," in 2009 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, 2009, pp. 2985-2988.
[73]
W. H. Minhass, J. Öberg and I. Sander, "Implementation of a scalable, globally plesiochronous locally synchronous, off-chip NoC communication protocol," in 2009 NORCHIP, 2009, pp. 1-5.
[74]
J. Zhu, I. Sander and A. Jantsch, "Energy efficient streaming applications with guaranteed throughput on MPSoCs," in Proceedings of the 7th ACM International Conference on Embedded Software, EMSOFT 2008, 2008, pp. 119-128.
[75]
J. Zhu, I. Sander and A. Jantsch, "Performance Analysis of Reconfiguration in Adaptive Real-Time Streaming Applications," in PROCEEDINGS OF THE 2008 IEEE/ACM/IFIP WORKSHOP ON EMBEDDED SYSTEMS FOR REAL-TIME MULTIMEDIA, 2008, pp. 53-58.
[76]
T. Raudvere, I. Sander and A. Jantsch, "A Synchronization Algorithm for Local Temporal Refinements in Perfectly Synchronous Models with Nested Feedback Loops," in GLSVLSI'07 : PROCEEDINGS OF THE 2007 ACM GREAT LAKES SYMPOSIUM ON VLSI, 2007, pp. 353-358.
[77]
A. Herrholz et al., "ANDRES : Analysis and Design of run-time Reconfigurable, heterogeneous Systems," in Workshop on Reconfigurable Systems at DATE, 2007.
[78]
T. Raudvere, I. Sander and A. Jantsch, "Synchronization after design refinements with sensitive delay elements," in Proceedings of the International Conference on HW/SW Codesign and System Synthesis, 2007.
[79]
A. Herrholz et al., "The ANDRES Project : Analysis and Design of run-time Reconfigurable, heterogeneous Systems," in Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL, 2007, pp. 396-401.
[80]
Z. Lu et al., "Using synchronizers for refining synchronous communication onto Hardware/Software architectures," in RSP 2007 : 18th IEEE/IFIP International Workshop on Rapid System Prototyping, Proceedings, 2007, pp. 143-149.
[81]
R. Thid, I. Sander and A. Jantsch, "Flexible bus and NoC performance analysis with configurable synthetic workloads," in DSD 2006 : 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, Proceedings, 2006, pp. 681-688.
[82]
Z. Lu, I. Sander and A. Jantsch, "Refining synchronous communication onto network-on-chip best-effort services," in Applications of Specification and Design Languages for SoCs, 2006, pp. 23-38.
[83]
J. Zhu, A. Jantsch and I. Sander, "SDF to Synchronous Cross Domain Analysis in ForSyDe Stream Processing Framework," in 2nd HiPEAC Industrial Workshop. Eindhoven, NL. October 2006, 2006.
[84]
Z. Lu, I. Sander and A. Jantsch, "Towards performance-oriented pattern-based refinement of synchronous models onto NoC communication," in DSD 2006: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, Proceedings, 2006, pp. 37-44.
[85]
Z. Lu, A. Jantsch and I. Sander, "Feasibility analysis of messages for on-chip networks using wormhole routing," in PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, pp. 960-964.
[86]
Z. Lu, I. Sander and A. Jantsch, "Refinement of A Perfectly Synchronous Communication Model onto Nostrum NoC Best-Effort Communication Service," in Proceedings of the Forum on Design Languages, 2005.
[87]
T. Raudvere et al., "System level verification of digital signal processing applications based on the polynomial abstraction technique," in ICCAD-2005 : International Conference On Computer Aided Design, Digest Of Technical Papers, 2005, pp. 285-290.
[88]
T. Raudvere et al., "Polynomial abstraction for verification of sequentially implemented combinational circuits," in DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, pp. 690-691.
[89]
I. Sander, A. Jantsch and H. Tenhunen, "The Platform as Interface in a SoC Design Curriculum," in Microelectronics Education : Proceedings of the 5th European Worksop on Microelectronics Education, 2004.
[90]
I. Sander, A. Jantsch and Z. Lu, "The Development and Application of Formal Design Transformations in ForSyDe," in Proceedings of the Design Automation and Test Europe (DATE), 2003.
[91]
T. Raudvere et al., "Verification of Design Decisions in ForSyDe," in Proceedings of the CODES-ISSS Conference, 2003.
[92]
Z. Lu, I. Sander and A. Jantsch, "A case study of hardware and software synthesis in ForSyDe," in Proceedings of the 15th International Symposium on System Synthesis, 2002.
[93]
T. Raudvere et al., "The ForSyDe semantics," in Proceedings of Swedish System-on-Chip Conference, 2002.
[94]
I. Sander and A. Jantsch, "Transformation Based Communication and Clock Domain Refinement for System Design," in Proceedings of Design Automation Conference, 2002.
[95]
A. Jantsch, I. Sander and W. Wu, "The Usage of Stochastic Processes in Embedded System Specifications," in Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001.
[96]
I. Sander, P. Kolodziejski and J.-P. Leibig, "Using a digital recording machine as the main thread in a project based electrical engineering curriculum," in Proceedings of the 31st ASEE/IEEE Frontiers in Education Conference (FIE 2001), 2001, pp. 14-19.
[97]
A. Jantsch and I. Sander, "On the Roles of Functions and Objects in System Specification," in Proceedings of the International Workshop on Hardware/Software Codesign, 2000.
[98]
W. Wu, I. Sander and A. Jantsch, "Transformational System Design based on a Formal Computational Model and Skeletons," in Proceedings of the Forum on Design Languages, 2000.
[99]
W. Wu, I. Sander and A. Jantsch, "Transformational System Design based on a Formal Computational Model and Skeletons," in Proceedings of the Forum on Design Languages, 2000.
[100]
I. Sander and A. Jantsch, "Formal Design Based on the Synchronous Approach, Functional Models and Skeletons," in Proceedings of the Twelfth International Conference on VLSI Design, 1999.
[101]
I. Sander and A. Jantsch, "System Synthesis Based on a Formal Computational Model and Skeletons," in Proceedings of the IEEE Computer Society Annual Workshop on VLSI, 1999.
[102]
I. Sander and A. Jantsch, "System Synthesis Utilizing a Layered Functional Model," in Proceedings of the 7th International Workshop on Hardware/Software Codesign, 1999, pp. 136-141.
[103]
A. Jantsch et al., "Comparison of Six Languages for System Level Descriptions of Telecom Systems," in Proceedings of the Forum on Design Languages, 1998.
Chapters in books
[104]
S. H. Attarzadeh Niaki, M. Mikulcak and I. Sander, "Automatic Generation of Virtual Prototypes from Platform Templates," in Languages, Design Methods, and Tools for Electronic System Design : Selected Contributions from FDL 2013, Marie-Minerve Louërat, Torsten Maehne Ed., Switzerland : Springer, 2015, pp. 147-166.
[105]
A. Jantsch and I. Sander, "Models of Computation in the Design Process," in System-on-Chip : Next Generation Electronics, Al-Hashimi, Bashir M. Ed., : Institution of Engineering and Technology, 2006, pp. 161-185.
Non-peer reviewed
Conference papers
[106]
R. Jordao et al., "Applying Constraint Programming for Design Space Exploration in Avionics," in Aerospace Technology Congress, 2019.
[107]
S. Penolazzi, I. Sander and A. Hemani, "Predicting bus contention effects on energy and performance in multi-processor SoCs," in 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011, 2011, pp. 1196-1199.
[108]
S. Penolazzi, I. Sander and A. Hemani, "Inferring energy and performance cost of RTOS in priority-driven scheduling," in 5th International Symposium on Industrial Embedded Systems, SIES 2010, 2010, pp. 1-8.
[109]
S. Penolazzi, I. Sander and A. Hemani, "Predicting energy and performance overhead of Real-Time Operating Systems," in Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, 2010, pp. 15-20.
Chapters in books
[110]
I. Sander, A. Jantsch and S. -. Attarzadeh-Niaki, "ForSyDe : System design using a functional language and models of computation," in Handbook of Hardware/Software Codesign, : Springer Netherlands, 2017, pp. 99-140.
[111]
S. -. Attarzadeh-Niaki et al., "A composable and predictable MPSoC design flow for multiple real-time applications," in Model-Implementation Fidelity in Cyber Physical System Design, : Springer International Publishing, 2016, pp. 157-174.
[112]
A. Jantsch et al., "A comparison of six languages for system level description of telecom applications," in Electronic Chips & System Design Languages, : Kluwer Academic Publishers, 2001, pp. 181-192.
Reports
[113]
B. Navas, I. Sander and J. Öberg, "Reinforcement Learning Based Self-Optimization of Dynamic Fault-Tolerant Schemes in Performance-Aware RecoBlock SoCs," Stockholm : KTH Royal Institute of Technology, TRITA-ICT/ECS, 15:27, 2015.
[114]
S. H. Attarzadeh Niaki et al., "A Framework for Characterizing Predictable Platform Templates," Stockholm, Sweden : KTH Royal Institute of Technology, TRITA-ICT/ECS R, 14:01, 2014.
[115]
P. Ellervee et al., "IRSYD - An Internal Representation for System Description. Version 0.1," ESDlab, KTH-Electrum, Electrum 229, S-16440 Kista, Sweden : Electronic System Design Laboratory, Department of Electronics, Royal Institute of Technology, 1997.
[116]
P. Ellervee et al., "IRSYD - An Internal Representation for System Description (Version 0.1)," , Trita-ESD, 1997-10, 1997.
Other
[117]
S.-H. Attarzadeh-Niaki and I. Sander, "An extensible modeling methodology for embedded and CPS design," (Manuscript).
[118]
S.-H. Attarzadeh-Niaki and I. Sander, "Automatic Construction of Models for Analytic Design Space Exploration Problems," (Manuscript).
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