Publikationer av Ingo Sander
Refereegranskade
Artiklar
[1]
R. Jordao, M. Becker och I. Sander, "IDeSyDe : Systematic Design Space Exploration via Design Space Identification," ACM Transactions on Design Automation of Electronic Systems, vol. 29, no. 5, 2024.
[2]
C. Schwartz et al., "Satellite Image Compression Guided by Regions of Interest," Sensors, vol. 23, no. 2, 2023.
[3]
S. -. Attarzadeh-Niaki, I. Sander och M. Ahmadi, "An automated parallel simulation flow for cyber-physical system design," Integration, vol. 77, s. 48-58, 2021.
[4]
D. S. Loubach et al., "Classification and Mapping of Model Elements for Designing Runtime Reconfigurable Systems," IEEE Access, vol. 9, s. 156337-156360, 2021.
[5]
G. Ungureanu et al., "ForSyDe-Atom : Taming Complexity in Cyber Physical System Design with Layers," ACM Transactions on Embedded Computing Systems, vol. 20, no. 2, 2021.
[6]
S. -. Attarzadeh-Niaki och I. Sander, "Heterogeneous co-simulation for embedded and cyber-physical systems design," Simulation (San Diego, Calif.), vol. 96, no. 9, s. 753-765, 2020.
[7]
R. Bonna et al., "Modeling and Simulation of Dynamic Applications Using Scenario-Aware Dataflow," ACM Transactions on Design Automation of Electronic Systems, vol. 24, no. 5, 2019.
[8]
K. Rosvall och I. Sander, "Flexible and Tradeoff-Aware Constraint-Based Design Space Exploration for Streaming Applications on Heterogeneous Platforms," ACM Transactions on Design Automation of Electronic Systems, vol. 23, no. 2, 2018.
[9]
K. Grüttner et al., "CONTREX : Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties," Microprocessors and microsystems, vol. 51, s. 39-55, 2017.
[10]
M. Fakih et al., "SAFEPOWER project : Architecture for safe and power-efficient mixed-criticality systems," Microprocessors and microsystems, vol. 52, s. 89-105, 2017.
[11]
S.-H. Attarzadeh-Niaki och I. Sander, "An extensible modeling methodology for embedded and cyber-physical system design," Simulation (San Diego, Calif.), vol. 92, no. 8, s. 771-794, 2016.
[12]
J. Zhu, I. Sander och A. Jantsch, "Performance Analysis of Reconfigurations in Adaptive Real-Time Streaming Applications," ACM Transactions on Embedded Computing Systems, vol. 11, no. 1, 2012.
[13]
T. Raudvere, I. Sander och A. Jantsch, "Application and. verification of local nonsemantic-preserving transformations in system-design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 6, s. 1091-1103, 2008.
[14]
I. Sander och A. Jantsch, "Modelling Adaptive Systems in ForSyDe," Electronic Notes in Theoretical Computer Science, vol. 200, no. 2, s. 39-54, 2008.
[15]
A. Jantsch och I. Sander, "Models of computation and languages for embedded system design," IEE Proceedings - Computers and digital Techniques, vol. 152, no. 2, s. 114-129, 2005.
[16]
I. Sander och A. Jantsch, "System modeling and transformational design refinement in ForSyDe," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 1, s. 17-32, 2004.
[17]
I. Sander, A. Jantsch och Z. Lu, "Development and application of design transformations in ForSyDe," IEE Proceedings - Computers and digital Techniques, vol. 150, no. 5, s. 313-320, 2003.
Konferensbidrag
[18]
R. Chen och I. Sander, "A Quantitative Type Approach to Formal Component-Based System Design," i 2024 forum on specification & design languages, FDL 2024, 2024, s. 27-36.
[19]
F. Bahrami et al., "Automatic Parallelization of Embedded Software via Hierarchical Process Network Transformations," i 2024 forum on specification & design languages, FDL 2024, 2024, s. 37-45.
[20]
R. Jordao et al., "Multi-objective preference-free exact design space exploration of static DSP on multicore platforms," i 2024 forum on specification & design languages, FDL 2024, 2024, s. 59-67.
[21]
R. Jordao et al., "Design space exploration for safe and optimal mapping of avionics functionality on IMA platforms," i AIAA/IEEE Digital Avionics Systems Conference : Proceedings, 2023.
[22]
R. Jordao et al., "A multi-view and programming language agnostic framework for model-driven engineering," i PROCEEDINGS OF THE 2022 FORUM ON SPECIFICATION & DESIGN LANGUAGES (FDL), 2022.
[23]
C. Schwartz et al., "On-board Satellite Data Processing to Achieve Smart Information Collection," i Proceedings of SPIE - The International Society for Optical Engineering, 2022.
[24]
I. Sander et al., "TOWARDS CORRECT-BY-CONSTRUCTION DESIGN OF SAFETY-CRITICAL EMBEDDED AVIONICS SYSTEMS," i 33rd Congress of the International Council of the Aeronautical Sciences, ICAS 2022, 2022, s. 1637-1658.
[25]
R. Jordao, I. Sander och M. Becker, "Formulation of Design Space Exploration Problems by Composable Design Space Identification," i PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021), 2021, s. 1204-1207.
[26]
G. Ungureanu, R. Jordao och I. Sander, "Exploiting Dataflow Models for Parallel Simulation of Discrete Timed Systems," i Proceedings of the 2020 Forum for Specification & Design Languages (FDL), 2020.
[27]
G. Ungureanu et al., "Formal design, co-simulation and validation of a radar signal processing system," i Proceedings of the 2019 Forum on Specification and Design Languages, FDL 2019, 2019.
[28]
Jose. E. G. de Medeiros, G. Ungureanu och I. Sander, "An Algebra for Modeling Continuous Time Systems," i PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2018, s. 861-864.
[29]
G. Ungureanu, J. E. G. de Medeiros och I. Sander, "Bridging Discrete and Continuous Time Models with Atoms," i PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2018, s. 277-280.
[30]
K. Rosvall et al., "Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors," i 2018 21st Euromicro Conference on Digital System Design (DSD), 2018.
[31]
G. Ungureanu och I. Sander, "A layered formal framework for modeling of cyber-physical systems," i Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, 2017, s. 1715-1720.
[32]
S. -. Attarzadeh-Niaki och I. Sander, "Automatic construction of models for analytic system-level design space exploration problems," i Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, 2017, s. 670-673.
[33]
K. Rosvall et al., "Throughput propagation in constraint-based design space exploration for mixed-criticality systems," i ACM International Conference Proceeding Series, 2017.
[34]
N. Khalilzad, K. Rosvall och I. Sander, "A modular design space exploration framework for multiprocessor real-time systems," i Forum on Specification and Design Languages, 2016.
[35]
R. Gorgen et al., "CONTREX : Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties," i 19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016), 2016, s. 286-293.
[36]
A. Lenz et al., "SAFEPOWER project : Architecture for Safe and Power-Efficient Mixed-Criticality Systems," i 19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016), 2016, s. 294-300.
[37]
G. Hjort Blindell, C. Menne och I. Sander, "Synthesizing Code for GPGPUs from abstract formal models," i 16th Conference on Languages, Design Methods, and Tools for Electronic System Design, FDL 2014, 2016, s. 115-134.
[38]
S.-H. Attarzadeh-Niaki et al., "A Composable and Predictable MPSoC Design Flow for Multiple Real-Time Applications," i 1st Workshop on Model-Implementation Fidelity (MiFi), March 13, 2015, Grenoble,France, 2015.
[39]
P. I. Diallo et al., "A formal, model-driven design flow for system simulation and multi-core implementation," i 2015 10th IEEE International Symposium on Industrial Embedded Systems, 2015, s. 254-263.
[40]
F. Herrera et al., "An efficient joint analytical and simulation-based design space exploration flow for predictable multi-core systems," i ACM International Conference Proceeding Series, 2015.
[41]
F. Herrera och I. Sander, "An extensible infrastructure for modeling and time analysis of predictable embedded systems," i Forum on Specification and Design Languages, 2015.
[42]
F. Herrera och I. Sander, "Combining analytical and simulation-based design space exploration for efficient time-critical and mixed-criticality systems," i Forum on Specification and Design Languages, FDL 2013, 2015, s. 167-188.
[43]
E. Paone et al., "Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints," i Proceedings -Design, Automation and Test in Europe, DATE, 2015, s. 736-741.
[44]
S. H. Attarzadeh-Niaki och I. Sander, "Integrating Functional Mock-up units into a formal heterogeneous system modeling framework," i 18th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2015, 2015.
[45]
B. Navas, I. Sander och J. Öberg, "Towards cognitive reconfigurable hardware : Self-aware learning in RTR fault-tolerant SoCs," i Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015, 2015.
[46]
K. Rosvall och I. Sander, "A constraint-based design space exploration framework for real-time applications on MPSoCs," i Proceedings -Design, Automation and Test in Europe, DATE 2014, 2014, s. 1-6.
[47]
B. Navas, J. Öberg och I. Sander, "On providing scalable self-healing adaptive fault-tolerance to RTR SoCs," i Proceedings of ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on, 2014, s. 1-6.
[48]
G. Hjort Blindell, C. Menne och I. Sander, "Synthesizing Code for GPGPUs from Abstract Formal Models," i Forum on specification and Design Languages (FDL), Munich, Germany, October 14-16, 2014, 2014.
[49]
B. Navas, J. Öberg och I. Sander, "The Upset-Fault-Observer : A Concept for Self-healing Adaptive Fault Tolerance," i Proceedings of the 2014 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2014, 2014, s. 89-96.
[50]
S. H. Attarzadeh Niaki och I. Sander, "An Automated Parallel Simulation Flow for Heterogeneous Embedded Systems," i Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013, s. 27-30.
[51]
F. Herrera och I. Sander, "Combining Analytical and Simulation-based Design Space Exploration for Time-Critical Systems," i Forum on Specification & Design Languages (FDL), 2013, 2013, s. 6646657.
[52]
G. Ungureanu et al., "Parallel software design enabling high-speed reliability testing of inkjet printheads," i International Conference on Digital Printing Technologies, 2013, s. 60-65.
[53]
S. H. Attarzadeh Niaki, M. Mikulcak och I. Sander, "Rapid virtual prototyping of real-time systems using predictable platform characterizations," i Forum on Specification Design Languages (FDL) 2013, 2013, s. 6646652.
[54]
S. Li et al., "System level synthesis of hardware for DSP applications using pre-characterized function implementations," i 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2013.
[55]
B. Navas, I. Sander och J. Öberg, "The RecoBlock SoC Platform : A Flexible Array of Reusable Run-Time-Reconfigurable IP-Blocks," i Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013, s. 833-838.
[56]
F. Herrera, H. Attarzadeh och I. Sander, "Towards a Modelling and Design Framework for Mixed-Criticality SoCs and Systems-of-Systems," i Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, 2013, s. 989-996.
[57]
B. Navas, J. Öberg och I. Sander, "Towards the generic reconfigurable accelerator : Algorithm development, core design, and performance analysis," i 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013; Cancun; Mexico, 2013, s. 1-6.
[58]
S. H. Attarzadeh Niaki et al., "Formal heterogeneous system modeling with SystemC," i Proceedings of Forum on Specification and Design Languages (FDL) 2012, 2012, s. 160-167.
[59]
S. H. Attarzadeh Niaki et al., "Heterogeneous system-level modeling for small and medium enterprises," i Integrated Circuits and Systems Design (SBCCI), 2012 25th Symposium on, 2012, s. 1-6.
[60]
G. S. Beserra, S. H. Attarzadeh Niaki och I. Sander, "Integrating virtual platforms into a heterogeneous MoC-based modeling framework," i Proceedings of Forum on Specification and Design Languages (FDL) 2012, 2012, s. 143-150.
[61]
S. H. Attarzadeh Niaki och I. Sander, "Co-simulation of embedded systems in a heterogeneous MoC-based modeling framework," i 2011 6th IEEE International Symposium on Industrial Embedded Systems (SIES) : Proceedings of a meeting held 15-17 June 2011, Vasteras, Sweden., 2011, s. 238-247.
[62]
S. H. Attarzadeh Niaki och I. Sander, "Semi-formal refinement of heterogeneous embedded systems by foreign model integration," i 2011 Forum on Specification and Design Languages (FDL), 2011, s. 179-186.
[63]
M. K. Jakobsen et al., "System level modelling with open source tools," i Embedded World Conference 2011, 2011.
[64]
I. Sander och S. H. Attarzadeh Niaki, "Towards a Formal Software Synthesis Methodology for Embedded Multiprocessor Systems," i Proceedings of First International Software Technology Exchange Workshop 2011, 2011.
[65]
J. Zhu, I. Sander och A. Jantsch, "Constrained Global Scheduling of Streaming Applications on MPSoCs," i 2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, s. 223-228.
[66]
J. Zhu, I. Sander och A. Jantsch, "HetMoC : Heterogeneous Modeling in SystemC," i Proceedings of the Forum on Design Langauges (FDL), 2010, s. 117-122.
[67]
J. Zhu, I. Sander och A. Jantsch, "Pareto Efficient Design for Reconfigurable Streaming Applications on CPU/FPGAs," i Proceedings of Design Automation and Test in Europe (DATE ’10), 2010, s. 1035-1040.
[68]
J. Zhu, I. Sander och A. Jantsch, "Buffer Minimization of Real-Time Streaming Applications Scheduling on Hybrid CPU/FPGA Architectures," i DATE : 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, 2009, s. 1506-1511.
[69]
B. Navas, I. Sander och J. Öberg, "Camera and LCM IP-Cores for NIOS SOPC System," i 6th FPGAworld Conference, Academic Proceedings 2009, 2009, s. 18-23.
[70]
W. H. Minhass, J. Öberg och I. Sander, "Design and implementation of a plesiochronous multi-core 4x4 network-on-chip FPGA platform with MPI HAL support," i 6th FPGAworld Conference, Academic Proceedings 2009, 2009, s. 52-57.
[71]
I. Sander, A. Acosta och A. Jantsch, "Hardware Design and Synthesis in ForSyDe," i Proceedings of Hardware Design and Functional Languages, 2009.
[72]
I. Sander et al., "High-Level Estimation and Trade-Off Analysis for Adaptive Real-Time Systems," i 2009 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, 2009, s. 2985-2988.
[73]
W. H. Minhass, J. Öberg och I. Sander, "Implementation of a scalable, globally plesiochronous locally synchronous, off-chip NoC communication protocol," i 2009 NORCHIP, 2009, s. 1-5.
[74]
J. Zhu, I. Sander och A. Jantsch, "Energy efficient streaming applications with guaranteed throughput on MPSoCs," i Proceedings of the 7th ACM International Conference on Embedded Software, EMSOFT 2008, 2008, s. 119-128.
[75]
J. Zhu, I. Sander och A. Jantsch, "Performance Analysis of Reconfiguration in Adaptive Real-Time Streaming Applications," i PROCEEDINGS OF THE 2008 IEEE/ACM/IFIP WORKSHOP ON EMBEDDED SYSTEMS FOR REAL-TIME MULTIMEDIA, 2008, s. 53-58.
[76]
T. Raudvere, I. Sander och A. Jantsch, "A Synchronization Algorithm for Local Temporal Refinements in Perfectly Synchronous Models with Nested Feedback Loops," i GLSVLSI'07 : PROCEEDINGS OF THE 2007 ACM GREAT LAKES SYMPOSIUM ON VLSI, 2007, s. 353-358.
[77]
A. Herrholz et al., "ANDRES : Analysis and Design of run-time Reconfigurable, heterogeneous Systems," i Workshop on Reconfigurable Systems at DATE, 2007.
[78]
T. Raudvere, I. Sander och A. Jantsch, "Synchronization after design refinements with sensitive delay elements," i Proceedings of the International Conference on HW/SW Codesign and System Synthesis, 2007.
[79]
A. Herrholz et al., "The ANDRES Project : Analysis and Design of run-time Reconfigurable, heterogeneous Systems," i Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL, 2007, s. 396-401.
[80]
Z. Lu et al., "Using synchronizers for refining synchronous communication onto Hardware/Software architectures," i RSP 2007 : 18th IEEE/IFIP International Workshop on Rapid System Prototyping, Proceedings, 2007, s. 143-149.
[81]
R. Thid, I. Sander och A. Jantsch, "Flexible bus and NoC performance analysis with configurable synthetic workloads," i DSD 2006 : 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, Proceedings, 2006, s. 681-688.
[82]
Z. Lu, I. Sander och A. Jantsch, "Refining synchronous communication onto network-on-chip best-effort services," i Applications of Specification and Design Languages for SoCs, 2006, s. 23-38.
[83]
J. Zhu, A. Jantsch och I. Sander, "SDF to Synchronous Cross Domain Analysis in ForSyDe Stream Processing Framework," i 2nd HiPEAC Industrial Workshop. Eindhoven, NL. October 2006, 2006.
[84]
Z. Lu, I. Sander och A. Jantsch, "Towards performance-oriented pattern-based refinement of synchronous models onto NoC communication," i DSD 2006: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, Proceedings, 2006, s. 37-44.
[85]
Z. Lu, A. Jantsch och I. Sander, "Feasibility analysis of messages for on-chip networks using wormhole routing," i PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, s. 960-964.
[86]
Z. Lu, I. Sander och A. Jantsch, "Refinement of A Perfectly Synchronous Communication Model onto Nostrum NoC Best-Effort Communication Service," i Proceedings of the Forum on Design Languages, 2005.
[87]
T. Raudvere et al., "System level verification of digital signal processing applications based on the polynomial abstraction technique," i ICCAD-2005 : International Conference On Computer Aided Design, Digest Of Technical Papers, 2005, s. 285-290.
[88]
T. Raudvere et al., "Polynomial abstraction for verification of sequentially implemented combinational circuits," i DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, s. 690-691.
[89]
I. Sander, A. Jantsch och H. Tenhunen, "The Platform as Interface in a SoC Design Curriculum," i Microelectronics Education : Proceedings of the 5th European Worksop on Microelectronics Education, 2004.
[90]
I. Sander, A. Jantsch och Z. Lu, "The Development and Application of Formal Design Transformations in ForSyDe," i Proceedings of the Design Automation and Test Europe (DATE), 2003.
[91]
T. Raudvere et al., "Verification of Design Decisions in ForSyDe," i Proceedings of the CODES-ISSS Conference, 2003.
[92]
Z. Lu, I. Sander och A. Jantsch, "A case study of hardware and software synthesis in ForSyDe," i Proceedings of the 15th International Symposium on System Synthesis, 2002.
[93]
T. Raudvere et al., "The ForSyDe semantics," i Proceedings of Swedish System-on-Chip Conference, 2002.
[94]
I. Sander och A. Jantsch, "Transformation Based Communication and Clock Domain Refinement for System Design," i Proceedings of Design Automation Conference, 2002.
[95]
A. Jantsch, I. Sander och W. Wu, "The Usage of Stochastic Processes in Embedded System Specifications," i Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001.
[96]
I. Sander, P. Kolodziejski och J.-P. Leibig, "Using a digital recording machine as the main thread in a project based electrical engineering curriculum," i Proceedings of the 31st ASEE/IEEE Frontiers in Education Conference (FIE 2001), 2001, s. 14-19.
[97]
A. Jantsch och I. Sander, "On the Roles of Functions and Objects in System Specification," i Proceedings of the International Workshop on Hardware/Software Codesign, 2000.
[98]
W. Wu, I. Sander och A. Jantsch, "Transformational System Design based on a Formal Computational Model and Skeletons," i Proceedings of the Forum on Design Languages, 2000.
[99]
W. Wu, I. Sander och A. Jantsch, "Transformational System Design based on a Formal Computational Model and Skeletons," i Proceedings of the Forum on Design Languages, 2000.
[100]
I. Sander och A. Jantsch, "Formal Design Based on the Synchronous Approach, Functional Models and Skeletons," i Proceedings of the Twelfth International Conference on VLSI Design, 1999.
[101]
I. Sander och A. Jantsch, "System Synthesis Based on a Formal Computational Model and Skeletons," i Proceedings of the IEEE Computer Society Annual Workshop on VLSI, 1999.
[102]
I. Sander och A. Jantsch, "System Synthesis Utilizing a Layered Functional Model," i Proceedings of the 7th International Workshop on Hardware/Software Codesign, 1999, s. 136-141.
[103]
A. Jantsch et al., "Comparison of Six Languages for System Level Descriptions of Telecom Systems," i Proceedings of the Forum on Design Languages, 1998.
Kapitel i böcker
[104]
S. H. Attarzadeh Niaki, M. Mikulcak och I. Sander, "Automatic Generation of Virtual Prototypes from Platform Templates," i Languages, Design Methods, and Tools for Electronic System Design : Selected Contributions from FDL 2013, Marie-Minerve Louërat, Torsten Maehne red., Switzerland : Springer, 2015, s. 147-166.
[105]
A. Jantsch och I. Sander, "Models of Computation in the Design Process," i System-on-Chip : Next Generation Electronics, Al-Hashimi, Bashir M. red., : Institution of Engineering and Technology, 2006, s. 161-185.
Icke refereegranskade
Konferensbidrag
[106]
R. Jordao et al., "Applying Constraint Programming for Design Space Exploration in Avionics," i Aerospace Technology Congress, 2019.
[107]
S. Penolazzi, I. Sander och A. Hemani, "Predicting bus contention effects on energy and performance in multi-processor SoCs," i 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011, 2011, s. 1196-1199.
[108]
S. Penolazzi, I. Sander och A. Hemani, "Inferring energy and performance cost of RTOS in priority-driven scheduling," i 5th International Symposium on Industrial Embedded Systems, SIES 2010, 2010, s. 1-8.
[109]
S. Penolazzi, I. Sander och A. Hemani, "Predicting energy and performance overhead of Real-Time Operating Systems," i Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, 2010, s. 15-20.
Kapitel i böcker
[110]
I. Sander, A. Jantsch och S. -. Attarzadeh-Niaki, "ForSyDe : System design using a functional language and models of computation," i Handbook of Hardware/Software Codesign, : Springer Netherlands, 2017, s. 99-140.
[111]
S. -. Attarzadeh-Niaki et al., "A composable and predictable MPSoC design flow for multiple real-time applications," i Model-Implementation Fidelity in Cyber Physical System Design, : Springer International Publishing, 2016, s. 157-174.
[112]
A. Jantsch et al., "A comparison of six languages for system level description of telecom applications," i Electronic Chips & System Design Languages, : Kluwer Academic Publishers, 2001, s. 181-192.
Rapporter
[113]
B. Navas, I. Sander och J. Öberg, "Reinforcement Learning Based Self-Optimization of Dynamic Fault-Tolerant Schemes in Performance-Aware RecoBlock SoCs," Stockholm : KTH Royal Institute of Technology, TRITA-ICT/ECS, 15:27, 2015.
[114]
S. H. Attarzadeh Niaki et al., "A Framework for Characterizing Predictable Platform Templates," Stockholm, Sweden : KTH Royal Institute of Technology, TRITA-ICT/ECS R, 14:01, 2014.
[115]
P. Ellervee et al., "IRSYD - An Internal Representation for System Description. Version 0.1," ESDlab, KTH-Electrum, Electrum 229, S-16440 Kista, Sweden : Electronic System Design Laboratory, Department of Electronics, Royal Institute of Technology, 1997.
[116]
P. Ellervee et al., "IRSYD - An Internal Representation for System Description (Version 0.1)," , Trita-ESD, 1997-10, 1997.
Övriga
[117]
S.-H. Attarzadeh-Niaki och I. Sander, "An extensible modeling methodology for embedded and CPS design," (Manuskript).
[118]
S.-H. Attarzadeh-Niaki och I. Sander, "Automatic Construction of Models for Analytic Design Space Exploration Problems," (Manuskript).
Senaste synkning med DiVA:
2024-12-22 02:54:14