| Lecture 1. Course introduction and motivation |
This lecture introduces the course objectives, course content and structure, and course assessment. We also motivate hardware acceleration for deep learning.
A hardware accelerator demo for real-time object detection will be shown in the first lecture.
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Visit and review all content in the Canvas course room.
Read slides for Lecture 1 in the Canvas course room.
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| Lecture 2. Linear regression and logistic regression |
This lecture introduces two basic statistical learning models starting from linear regression to logistic regression. |
Pre-review slides for Lecture 2 in the Canvas course room. |
| Lecture 3. Perceptron and Multi-Layer Perceptron (MLP) |
This lecture discusses the general concepts of artificial neural networks (ANNs) from perceptron to multi-layer perceptron (MLP), in particular, about network training and inference. |
Pre-review slides for Lecture 3 in the Canvas course room. |
| Lecture 4. Lecture 4 CNN (Convolutional Neural Network) |
This lecture presents Convolutional Neural Network as one very successful example of Deep Neural Networks (DNNs). |
Pre-review slides for Lecture 4 in the Canvas course room. |
| Lab 1. Handwritten Digits Recognition from MLP to CNN |
This lab prepares you with the necessary skills and knowledge for performing basic deep-learning tasks in PyTorch. In particular, you are going to realize handwritten digits recognition using MLP and CNN and compare their performance.
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Try to finish the lab tasks as much as you can. |
| Lecture 5. RNN (Recurrent Neural Network) |
This lecture presents another important category of DNN with feedback in its structure, namely Recurrent Neural Network (RNN) which considers neuron interactions over time with memory effect. This includes both conventional RNN and LSTM. |
Pre-review slides for Lecture 5 in the Canvas course room. |
| Lecture 6. Hardware acceleration for deep learning: Challenges and Overview; Model minimization I |
This lecture discusses the efficiency challenges (performance, power/energy, resource) of executing deep learning algorithms on hardware, and opens the problem space for hardware acceleration of deep learning algorithms. We discuss the model minimization issues such as network reduction, data quantization, compression, fixed-point operations, etc. for efficient hardware implementations of neural network algorithms. |
Pre-review slides for Lecture 6 in the Canvas course room. |
| Lecture 7. Model minimization II |
This lecture continues discussing the latest model minimization techniques: Network pruning, Data quantization and approximation, and Network sparsity. |
Pre-review slides for Lecture 7 in the Canvas course room. |
| Lecture 8. Hardware Specialization I |
This lecture discusses hardware specializations for neural network algorithms, focusing on digital hardware design organization and computing architecture design principles. It also investigates network sparsity and sparsity acceleration. |
Pre-review slides for Lecture 8 in the Canvas course room. |
| Seminar I. Deep Learning and Minimization of Neural Network Models |
A workshop in a conference setting. Each student group is both a presenter (presenting its assigned paper) and an opponent (asking questions to another group). |
Read the assigned paper, prepare presentation slides as a group, and prepare questions for another group. |
| Lab 2. Hardware Design, Implementation and Evaluation of Artificial Neuron |
In this lab, the tasks are to design three RTL models (three alternative ways) for implementing an N-input artificial neuron. After you verify their correct functionality, you bring the designs for logic synthesis. |
Try to finish the lab tasks as much as you can. |
| Lecture 9. Hardware specialization II |
This lecture continues to discuss latest techniques used for hardware acceleration: the tile-based architecture, data flow schemes, and ASIP (application-specific instruction-set processor). |
Pre-review slides for Lecture 9 in the Canvas course room. |
| Lecture 10. Model-to-Architecture Mapping and EDA; Technology-Driven DL Acceleration and Brain-like Computing |
This lecture discusses model-to-architecture mapping, its optimization, and Electronic Design Automation (EDA). It also gives an outlook of efficient hardware acceleration of neural networks, with a focus on impacts from technology such as embedded DRAM, 3D stacking, memristor, etc. We also touch upon neuromorphic computing with spiking neural network. |
Pre-review slides for Lecture 10 in the Canvas course room. |
| Exercise |
This is an exercise Q & A session. The exercise questions are collected in an exercise compendium. The questions cover all lectures. |
Finish the exercise questions individually before the exercise session. |
| Lab 3 |
For this lab, you can choose one of the two tasks: (A) Hardware design, implementation and evaluation of MLP; (B) Transfer Learning, Network Pruning and Quantization. |
Try to finish the lab tasks as much as you can. |
| Seminar II. Case studies of deep learning hardware accelerators |
A workshop in a conference setting. Each student group is both a presenter (presenting its assigned paper) and an opponent (asking questions to another group). |
Read the assigned paper, prepare presentation slides as a group, and prepare questions for another group. |
