ULTRA ERC

Recruitments in the winter of 2019/2020

Dejan Kostic2020-01-07

I am looking for an excellent postdoc to join our team, you can see more details and apply here.

I am also looking for more doctoral students to join this exciting project, the ad and link to apply is here.

Our upcoming CoNEXT 2019 paper “RSS++: load and state-aware receive side scaling”

Dejan Kostic2019-12-022019-12-03

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While the current literature typically focuses on load-balancing among multiple servers, in our upcoming CoNEXT 2019 paper, we demonstrate the importance of load-balancing within a single machine (potentially with hundreds of CPU cores). In this context, we propose a new load-balancing technique (RSS++) that dynamically modifies the receive side scaling (RSS) indirection table to spread the load across the CPU cores in a more optimal way. RSS++ incurs up to 14x lower 95th percentile tail latency and orders of magnitude fewer packet drops compared to RSS under high CPU utilization. RSS++ allows higher CPU utilization and dynamic scaling of the number of allocated CPU cores to accommodate the input load, while avoiding the typical 25% over-provisioning. RSS++ has been implemented for both (i) DPDK and (ii) the Linux kernel. Additionally, we implement a new state migration technique, which facilitates sharding and reduces contention between CPU cores accessing per-flow data. RSS++ keeps the flow-state by groups that can be migrated at once, leading to a 20% higher efficiency than a state of the art shared flow table.

This is joint work with Tom Barbette, Georgios P. Katsikas, Gerald Q. Maguire Jr., and Dejan Kostic

Recruitments in the summer of 2019

Dejan Kostic2019-05-312019-06-15

I am looking for an excellent postdoc to join our team, you can see more details and apply here.

I am also looking for more doctoral students to join this exciting project, the ad and link to apply is here.

Our Upcoming EuroSys 2019 Paper “Make the Most out of Last Level Cache in Intel Processors”

Dejan Kostic2019-03-08

In our upcoming EuroSys 2019 paper, we exploit the characteristics of non-uniform cache architecture (NUCA) in recent Intel processors to introduce a new memory management scheme, i.e., slice-aware memory management. We believe that we are the first to: (i) take a step toward using the current hardware more efficiently in this manner, and (ii) advocate taking advantage of NUCA characteristics in LLC and allowing networking applications to benefit from it. In addition, we propose CacheDirector, a network I/O solution which extends Direct Data I/O (DDIO) and places the packet’s header in the slice of the LLC that is closest to the relevant processing core. The results of our work showed that CacheDirector could reduce the tail latencies in latency-critical Network Function Virtualization (NFV) service chains by 21.5%. Furthermore, our work demonstrated that optimizing the computer systems and taking advantage of nanosecond improvements could have a higher impact on the performance of networking applications.

ULTRA

Dejan Kostic2018-09-132021-11-03

This is the official blog/website for the ULTRA ERC Project. More details are avaiable in the Mission (with a summary updated in January 2021) and Publications pages.