CacheDirector Again in the News
Following an in-depth news article at the KTH School of EECS, CacheDirector is appearing in wider tech news circles, such as TechXplore, and AlphaGallileo.
Following an in-depth news article at the KTH School of EECS, CacheDirector is appearing in wider tech news circles, such as TechXplore, and AlphaGallileo.
We are happy to announce that Alireza Farshin successfully defended his licentiate thesis (licentiate is a degree at KTH half-way to a PhD)! We are once again very grateful to Prof. Gerald Q. Maguire Jr. for a fantastic co-advising job. Prof. Babak Falsafi was a superb opponent at the licentiate seminar. Alireza’s thesis is available … Continue reading “Alireza Farshin’s Licentiate Defense”
On March 26, 2019 in Dresden, Alireza Farshin presented our EuroSys 2019 paper on unlocking a performance-enhancing feature that existed in Intel processors for almost a decade. We are making the video of the talk available. The slides are available as well. CPUs typically have cache memory which increases the speed of access for the … Continue reading “Video of our presentation at EuroSys 2019: “Make the Most out of Last Level Cache in Intel Processors””
Our work on unlocking the performance-enhancing last-level cache feature of recent Intel processors is starting to make the news! You can follow the news here: Ericsson, KTH Research, KTH Research (in Swedish), and you can also join the technical discussion on Dejan’s Facebook post. The full EuroSys 2019 paper is available here.
In our upcoming EuroSys 2019 paper, we exploit the characteristics of non-uniform cache architecture (NUCA) in recent Intel processors to introduce a new memory management scheme, i.e., slice-aware memory management. We believe that we are the first to: (i) take a step toward using the current hardware more efficiently in this manner, and (ii) advocate … Continue reading “Our Upcoming EuroSys 2019 Paper “Make the Most out of Last Level Cache in Intel Processors””