Our Upcoming EuroSys 2019 Paper “Make the Most out of Last Level Cache in Intel Processors”
In our upcoming EuroSys 2019 paper, we exploit the characteristics of non-uniform cache architecture (NUCA) in recent Intel processors to introduce a new memory management scheme, i.e., slice-aware memory management. We believe that we are the first to: (i) take a step toward using the current hardware more efficiently in this manner, and (ii) advocate … Continue reading “Our Upcoming EuroSys 2019 Paper “Make the Most out of Last Level Cache in Intel Processors””