Class information for: |
Basic class information |
ID | Publications | Average number of references |
Avg. shr. active ref. in WoS |
---|---|---|---|
8977 | 1132 | 14.4 | 48% |
Classes in level above (level 2) |
ID, lev. above |
Publications | Label for level above |
---|---|---|
1951 | 5180 | IEEE JOURNAL OF SOLID-STATE CIRCUITS//CLOCK AND DATA RECOVERY CDR//PHASE LOCKED LOOP PLL |
Terms with highest relevance score |
Rank | Term | Type of term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|---|
1 | CLOCK AND DATA RECOVERY CDR | Author keyword | 76 | 63% | 7% | 77 |
2 | CLOCK AND DATA RECOVERY | Author keyword | 49 | 57% | 5% | 58 |
3 | JITTER TOLERANCE | Author keyword | 25 | 63% | 2% | 25 |
4 | SERIAL LINK | Author keyword | 24 | 48% | 3% | 36 |
5 | BANG BANG PLL | Author keyword | 15 | 88% | 1% | 7 |
6 | BANG BANG PHASE DETECTOR BBPD | Author keyword | 14 | 100% | 1% | 7 |
7 | CROSSTALK INDUCED JITTER | Author keyword | 14 | 100% | 1% | 7 |
8 | CROSSTALK INDUCED JITTER CIJ | Author keyword | 14 | 100% | 1% | 7 |
9 | SINGLE ENDED SIGNALING | Author keyword | 13 | 71% | 1% | 10 |
10 | VOLTAGE MODE DRIVER | Author keyword | 12 | 86% | 1% | 6 |
Web of Science journal categories |
Author Key Words |
Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
LCSH search | Wikipedia search |
---|---|---|---|---|---|---|---|
1 | CLOCK AND DATA RECOVERY CDR | 76 | 63% | 7% | 77 | Search CLOCK+AND+DATA+RECOVERY+CDR | Search CLOCK+AND+DATA+RECOVERY+CDR |
2 | CLOCK AND DATA RECOVERY | 49 | 57% | 5% | 58 | Search CLOCK+AND+DATA+RECOVERY | Search CLOCK+AND+DATA+RECOVERY |
3 | JITTER TOLERANCE | 25 | 63% | 2% | 25 | Search JITTER+TOLERANCE | Search JITTER+TOLERANCE |
4 | SERIAL LINK | 24 | 48% | 3% | 36 | Search SERIAL+LINK | Search SERIAL+LINK |
5 | BANG BANG PLL | 15 | 88% | 1% | 7 | Search BANG+BANG+PLL | Search BANG+BANG+PLL |
6 | BANG BANG PHASE DETECTOR BBPD | 14 | 100% | 1% | 7 | Search BANG+BANG+PHASE+DETECTOR+BBPD | Search BANG+BANG+PHASE+DETECTOR+BBPD |
7 | CROSSTALK INDUCED JITTER | 14 | 100% | 1% | 7 | Search CROSSTALK+INDUCED+JITTER | Search CROSSTALK+INDUCED+JITTER |
8 | CROSSTALK INDUCED JITTER CIJ | 14 | 100% | 1% | 7 | Search CROSSTALK+INDUCED+JITTER+CIJ | Search CROSSTALK+INDUCED+JITTER+CIJ |
9 | SINGLE ENDED SIGNALING | 13 | 71% | 1% | 10 | Search SINGLE+ENDED+SIGNALING | Search SINGLE+ENDED+SIGNALING |
10 | VOLTAGE MODE DRIVER | 12 | 86% | 1% | 6 | Search VOLTAGE+MODE+DRIVER | Search VOLTAGE+MODE+DRIVER |
Key Words Plus |
Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|
1 | SERIAL LINK | 29 | 71% | 2% | 24 |
2 | BACKPLANE TRANSCEIVER | 27 | 83% | 1% | 15 |
3 | TRANSCEIVER | 27 | 17% | 13% | 147 |
4 | DATA RECOVERY CIRCUIT | 23 | 48% | 3% | 35 |
5 | INDUCED JITTER | 12 | 86% | 1% | 6 |
6 | CDR | 10 | 46% | 1% | 16 |
7 | CMOS CLOCK | 9 | 55% | 1% | 12 |
8 | SERIAL LINKS | 8 | 75% | 1% | 6 |
9 | WIRELESS SUPERCONNECT | 8 | 100% | 0% | 5 |
10 | DATA RECOVERY | 8 | 38% | 1% | 16 |
Journals |
Reviews |
Title | Publ. year | Cit. | Active references |
% act. ref. to same field |
---|---|---|---|---|
Design techniques for decision feedback equalisation of multi-giga-bit-per-second serial data links: a state-of-the-art review | 2014 | 0 | 46 | 93% |
Address terms |
Rank | Address term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|
1 | DRAM DESIGN | 6 | 50% | 0.7% | 8 |
2 | KURODA | 3 | 100% | 0.3% | 3 |
3 | ARAGON ENGN GDE I3A | 3 | 60% | 0.3% | 3 |
4 | SAMSUNG RFIC DESIGN | 2 | 67% | 0.2% | 2 |
5 | GRP ELECT DESIGN | 2 | 25% | 0.5% | 6 |
6 | DRAM DESIGN TEAM | 2 | 28% | 0.4% | 5 |
7 | SOLID STATE CIRCUIT | 1 | 100% | 0.2% | 2 |
8 | INTEC DESIGN | 1 | 40% | 0.2% | 2 |
9 | AISL | 1 | 33% | 0.2% | 2 |
10 | MICROPROCESSOR TECHNOL S | 1 | 33% | 0.2% | 2 |
Related classes at same level (level 1) |
Rank | Relatedness score | Related classes |
---|---|---|
1 | 0.0000222125 | TIME TO DIGITAL CONVERTER TDC//DIGITALLY CONTROLLED OSCILLATOR DCO//ALL DIGITAL PHASE LOCKED LOOP ADPLL |
2 | 0.0000170567 | DECISION CIRCUITS//DEMULTIPLEXING EQUIPMENT//MIKROELEKT ZENTRUM A |
3 | 0.0000166897 | TRANSIMPEDANCE AMPLIFIER TIA//TRANSIMPEDANCE AMPLIFIER//ELE ODYNAM MICROWAVE CIRCUIT ENGN |
4 | 0.0000072185 | VOLTAGE CONTROLLED OSCILLATOR VCO//PHASE NOISE//LOCKING RANGE |
5 | 0.0000060396 | ANALOG TO DIGITAL CONVERTER ADC//DIGITAL BACKGROUND CALIBRATION//PIPELINED ADC |
6 | 0.0000058138 | CURRENT STEERING//DIGITAL TO ANALOG CONVERTER DAC//DIGITAL TO ANALOG CONVERTERS DACS |
7 | 0.0000056354 | LEVEL CROSSING SAMPLING//CHANNEL IDENTIFICATION MACHINES//TIME ENCODING MACHINES |
8 | 0.0000054352 | LINE DRIVER//OPERAT SYST DEV//RADIO COMMUN NETWORKS S RADIO COMMUN SYST |
9 | 0.0000054129 | SUBSTRATE NOISE//SUBSTRATE COUPLING//POWER SUPPLY NOISE |
10 | 0.0000054122 | CLOCK TREE//CLOCK SKEW//CLOCK DISTRIBUTION |