Class information for:
Level 1: FLOORPLANNING//PHYSICAL DESIGN//PLACEMENT

Basic class information
ID Publications Average number
of references		 Avg. shr. active
ref. in WoS
7483 1283 22.2 27%


Bar chart of Publication_year

Last years might be incomplete

Classes in level above (level 2)


ID, lev.
above		 Publications Label for level above
2570 3228 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//FLOORPLANNING//PHYSICAL DESIGN

Terms with highest relevance score


Rank Term Type of term Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class
1 FLOORPLANNING Author keyword 48 40% 7% 93
2 PHYSICAL DESIGN Author keyword 31 26% 8% 101
3 PLACEMENT Author keyword 21 16% 9% 120
4 GLOBAL ROUTING Author keyword 18 34% 3% 44
5 RENTS RULE Author keyword 13 46% 2% 22
6 FINE GRAIN RECONFIGURABLE VLSI Author keyword 12 86% 0% 6
7 ROUTABILITY Author keyword 9 36% 2% 21
8 FIXED OUTLINE Author keyword 9 67% 1% 8
9 STANDARD CELL PLACEMENT Author keyword 9 67% 1% 8
10 INTERCONNECT ESTIMATION Author keyword 8 75% 0% 6

Web of Science journal categories

Author Key Words


Rank Web of Science journal category Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class		 LCSH search Wikipedia search
1 FLOORPLANNING 48 40% 7% 93 Search FLOORPLANNING Search FLOORPLANNING
2 PHYSICAL DESIGN 31 26% 8% 101 Search PHYSICAL+DESIGN Search PHYSICAL+DESIGN
3 PLACEMENT 21 16% 9% 120 Search PLACEMENT Search PLACEMENT
4 GLOBAL ROUTING 18 34% 3% 44 Search GLOBAL+ROUTING Search GLOBAL+ROUTING
5 RENTS RULE 13 46% 2% 22 Search RENTS+RULE Search RENTS+RULE
6 FINE GRAIN RECONFIGURABLE VLSI 12 86% 0% 6 Search FINE+GRAIN+RECONFIGURABLE+VLSI Search FINE+GRAIN+RECONFIGURABLE+VLSI
7 ROUTABILITY 9 36% 2% 21 Search ROUTABILITY Search ROUTABILITY
8 FIXED OUTLINE 9 67% 1% 8 Search FIXED+OUTLINE Search FIXED+OUTLINE
9 STANDARD CELL PLACEMENT 9 67% 1% 8 Search STANDARD+CELL+PLACEMENT Search STANDARD+CELL+PLACEMENT
10 INTERCONNECT ESTIMATION 8 75% 0% 6 Search INTERCONNECT+ESTIMATION Search INTERCONNECT+ESTIMATION

Key Words Plus


Rank Web of Science journal category Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class
1 PROGRAMMABLE GATE ARRAYS 11 33% 2% 29
2 GLOBAL ROUTER 11 78% 1% 7
3 REDUCTION DESIGN 6 71% 0% 5
4 ROUTABILITY 5 54% 1% 7
5 AREA MINIMIZATION 5 63% 0% 5
6 GENERAL FLOORPLANS 5 63% 0% 5
7 TCG 5 55% 0% 6
8 B ASTERISK TREES 4 67% 0% 4
9 FPGA DESIGNS 4 75% 0% 3
10 AREA OPTIMIZATION 4 56% 0% 5

Journals


Rank Web of Science journal category Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class
1 ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 3 12% 2% 21

Reviews


Title Publ. year Cit. Active
references		 % act. ref.
to same field
RECENT DIRECTIONS IN NETLIST PARTITIONING - A SURVEY 1995 209 34 59%
Physical limits of silicon transistors and circuits 2005 34 44 25%
Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements 2005 10 38 53%
Tutorial on VLSI partitioning 2000 3 30 67%
Mathematical methods for physical layout of printed circuit boards: an overview 2008 0 28 36%
PHYSICAL LIMITS IN INFORMATION-PROCESSING 1988 1 15 13%

Address terms


Rank Address term Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ.
in class
1 PLACEMENT TECHNOL GRP 3 100% 0.2% 3
2 TORONTO TECHNOL 3 100% 0.2% 3
3 INT ENVIRONM ENGN 2 44% 0.3% 4
4 DESIGN PROD GRP 2 67% 0.2% 2
5 PROMOT DEV OFF 2 67% 0.2% 2
6 VLSI SYST DESIGN 2 33% 0.3% 4
7 RUG ELIS 1 100% 0.2% 2
8 ENTERPRISE MICROPROCESSOR GRP 1 40% 0.2% 2
9 ETISALAT ENGN 1 40% 0.2% 2
10 FUJIAN PROV NETWORK COMP INTELLIGENT IN 1 40% 0.2% 2

Related classes at same level (level 1)


Rank Relatedness score Related classes
1 0.0000180673 CHANNEL ROUTING//OVER THE CELL ROUTING//VLSI LAYOUT
2 0.0000129219 COOLING SCHEDULES//FINITE TIME PERFORMANCE//ADAPTIVE COOLING SCHEDULE
3 0.0000121065 SYST LEVEL INTEGRAT GRP//DYNAMIC PARTIAL RECONFIGURATION DPR//DYNAMICALLY PROGRAMMABLE GATE ARRAY
4 0.0000111845 STEINER RATIO//INVERSE FERMAT TORRICELLI PROBLEM//STEINER MINIMAL TREE
5 0.0000099260 RECONFIGURABLE COMPUTING//INSTRUCTION SET EXTENSION ISE//ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS
6 0.0000099024 ANALOG CIRCUIT SYNTHESIS//CIRCUIT SIZING//ANALOG DESIGN AUTOMATION
7 0.0000089554 STATE ASSIGNMENT//FSM SYNTHESIS//LOGIC SYNTHESIS
8 0.0000088093 THROUGH SILICON VIA TSV//3 D INTEGRATION//KEEP OUT ZONE KOZ
9 0.0000072829 GUILLOTINE PARTITIONS//SORTABILITY//MOSAIC FLOORPLAN
10 0.0000068466 CLOCK TREE//CLOCK SKEW//CLOCK DISTRIBUTION