Class information for: |
Basic class information |
ID | Publications | Average number of references |
Avg. shr. active ref. in WoS |
---|---|---|---|
3979 | 1795 | 20.5 | 41% |
Classes in level above (level 2) |
ID, lev. above |
Publications | Label for level above |
---|---|---|
923 | 10486 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//HIGH LEVEL SYNTHESIS |
Terms with highest relevance score |
Rank | Term | Type of term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|---|
1 | SRAM | Author keyword | 48 | 22% | 11% | 198 |
2 | PROCESS VARIATION | Author keyword | 26 | 21% | 6% | 112 |
3 | POWER GATING | Author keyword | 24 | 30% | 4% | 68 |
4 | STATIC RANDOM ACCESS MEMORY SRAM | Author keyword | 17 | 36% | 2% | 38 |
5 | SUBTHRESHOLD LEAKAGE | Author keyword | 16 | 49% | 1% | 24 |
6 | PROCESS VARIATIONS | Author keyword | 15 | 21% | 4% | 64 |
7 | MTCMOS | Author keyword | 14 | 38% | 2% | 30 |
8 | DUAL THRESHOLD VOLTAGE | Author keyword | 14 | 57% | 1% | 17 |
9 | VOLTAGE SCALING | Author keyword | 13 | 28% | 2% | 40 |
10 | LEAKAGE POWER | Author keyword | 11 | 21% | 3% | 46 |
Web of Science journal categories |
Author Key Words |
Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
LCSH search | Wikipedia search |
---|---|---|---|---|---|---|---|
1 | SRAM | 48 | 22% | 11% | 198 | Search SRAM | Search SRAM |
2 | PROCESS VARIATION | 26 | 21% | 6% | 112 | Search PROCESS+VARIATION | Search PROCESS+VARIATION |
3 | POWER GATING | 24 | 30% | 4% | 68 | Search POWER+GATING | Search POWER+GATING |
4 | STATIC RANDOM ACCESS MEMORY SRAM | 17 | 36% | 2% | 38 | Search STATIC+RANDOM+ACCESS+MEMORY+SRAM | Search STATIC+RANDOM+ACCESS+MEMORY+SRAM |
5 | SUBTHRESHOLD LEAKAGE | 16 | 49% | 1% | 24 | Search SUBTHRESHOLD+LEAKAGE | Search SUBTHRESHOLD+LEAKAGE |
6 | PROCESS VARIATIONS | 15 | 21% | 4% | 64 | Search PROCESS+VARIATIONS | Search PROCESS+VARIATIONS |
7 | MTCMOS | 14 | 38% | 2% | 30 | Search MTCMOS | Search MTCMOS |
8 | DUAL THRESHOLD VOLTAGE | 14 | 57% | 1% | 17 | Search DUAL+THRESHOLD+VOLTAGE | Search DUAL+THRESHOLD+VOLTAGE |
9 | VOLTAGE SCALING | 13 | 28% | 2% | 40 | Search VOLTAGE+SCALING | Search VOLTAGE+SCALING |
10 | LEAKAGE POWER | 11 | 21% | 3% | 46 | Search LEAKAGE+POWER | Search LEAKAGE+POWER |
Key Words Plus |
Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|
1 | SUBTHRESHOLD SRAM | 39 | 63% | 2% | 40 |
2 | 8T SRAM | 13 | 71% | 1% | 10 |
3 | SRAM | 12 | 20% | 3% | 53 |
4 | BODY BIAS | 12 | 37% | 1% | 25 |
5 | BITLINE | 11 | 100% | 0% | 6 |
6 | VARIATION TOLERANCE | 11 | 100% | 0% | 6 |
7 | LOW VOLTAGE OPERATION | 9 | 55% | 1% | 12 |
8 | BIT LINE | 8 | 70% | 0% | 7 |
9 | NANOSCALED CMOS | 8 | 70% | 0% | 7 |
10 | MTCMOS CIRCUITS | 8 | 75% | 0% | 6 |
Journals |
Reviews |
Title | Publ. year | Cit. | Active references |
% act. ref. to same field |
---|---|---|---|---|
Statistical timing analysis: From basic principles to state of the art | 2008 | 95 | 6 | 33% |
Digital circuit design challenges and opportunities in the era of nanoscale CMOS | 2008 | 32 | 51 | 39% |
Statistical static timing analysis: A survey | 2009 | 8 | 8 | 50% |
Precomputation-based guarding and a robust power gating strategy in deep sub-micron CMOS | 2007 | 0 | 6 | 83% |
Review and future prospects of low-voltage RAM circuits | 2003 | 36 | 25 | 44% |
Timing Analysis Techniques Review for sub-30 nm Circuit Designs | 2010 | 0 | 6 | 50% |
Energy efficient computation: A silicon perspective | 2014 | 0 | 7 | 43% |
Review of low-voltage CMOS LSI technology as a standard in the 21st century | 1998 | 0 | 13 | 62% |
Computer-aided design for low-power robust computing in nanoscale CMOS | 2007 | 4 | 18 | 28% |
Serial addition: Locally connected architectures | 2007 | 5 | 43 | 19% |
Address terms |
Rank | Address term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|
1 | ADV DESIGN DIGITAL CIRCUITS TECHNOL INTEGRAT | 3 | 100% | 0.2% | 3 |
2 | INTEGRATED CIRCUITS ELECT | 3 | 100% | 0.2% | 3 |
3 | LOW POWER CIRCUITS SYST | 3 | 100% | 0.2% | 3 |
4 | CIRCUIT | 3 | 25% | 0.6% | 11 |
5 | CIRCUITS | 3 | 32% | 0.4% | 8 |
6 | LOW POWER CIRCUITS SYST LPCS | 2 | 67% | 0.1% | 2 |
7 | VISUAL PARALLEL COMP GRP | 2 | 67% | 0.1% | 2 |
8 | MICROPROCESSOR S | 2 | 30% | 0.3% | 6 |
9 | ADV DESIGN GRP | 2 | 50% | 0.2% | 3 |
10 | GR H PERFORMANCE GRP 3D | 1 | 100% | 0.1% | 2 |
Related classes at same level (level 1) |
Rank | Relatedness score | Related classes |
---|---|---|
1 | 0.0000240769 | DEVICE MODELLING GRP//RANDOM DOPANT//DEVICE MODELING GRP |
2 | 0.0000225662 | SHORT CIRCUIT POWER DISSIPATION//TRANSISTOR SIZING//GATE SIZING |
3 | 0.0000166755 | CLOCK TREE//CLOCK SKEW//CLOCK DISTRIBUTION |
4 | 0.0000162289 | DATA RETENTION TIME//VOLTAGE DOWN CONVERTER//FERROELECTRIC MEMORY |
5 | 0.0000143380 | ADIABATIC CIRCUIT//ADIABATIC CHARGING//ENERGY RECOVERY LOGIC |
6 | 0.0000140512 | NEGATIVE BIAS TEMPERATURE INSTABILITY NBTI//NEGATIVE BIAS TEMPERATURE INSTABILITY//CHRISTIAN DOPPLER TCAD |
7 | 0.0000135810 | POWER ESTIMATION//SWITCHING ACTIVITY//BUS ENCODING |
8 | 0.0000129207 | PASS TRANSISTOR LOGIC//DIGITAL ARITHMETIC//FIXED WIDTH MULTIPLIER |
9 | 0.0000123808 | SUBSTRATE NOISE//SUBSTRATE COUPLING//POWER SUPPLY NOISE |
10 | 0.0000086058 | COUPLED METHOD CM//MICROPARTICLE MANIPULATION//LEVELIZED |