Class information for: |
Basic class information |
ID | Publications | Average number of references |
Avg. shr. active ref. in WoS |
---|---|---|---|
3901 | 1812 | 24.7 | 23% |
Classes in level above (level 2) |
ID, lev. above |
Publications | Label for level above |
---|---|---|
326 | 17471 | PARALLEL COMPUTING//JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING//INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING |
Terms with highest relevance score |
Rank | Term | Type of term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|---|
1 | ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION | Journal | 24 | 25% | 5% | 84 |
2 | IEEE MICRO | Journal | 19 | 12% | 8% | 145 |
3 | BRANCH PREDICTION | Author keyword | 19 | 34% | 2% | 45 |
4 | VALUE PREDICTION | Author keyword | 15 | 50% | 1% | 22 |
5 | THREAD LEVEL SPECULATION | Author keyword | 13 | 46% | 1% | 22 |
6 | SIMULTANEOUS MULTITHREADING | Author keyword | 12 | 39% | 1% | 25 |
7 | CACHE MEMORY | Author keyword | 12 | 24% | 2% | 42 |
8 | BRANCH TARGET BUFFER | Author keyword | 12 | 54% | 1% | 15 |
9 | ENGN MICROPROCESSOR SYST | Address | 9 | 83% | 0% | 5 |
10 | RUNAHEAD EXECUTION | Author keyword | 9 | 83% | 0% | 5 |
Web of Science journal categories |
Author Key Words |
Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
LCSH search | Wikipedia search |
---|---|---|---|---|---|---|---|
1 | BRANCH PREDICTION | 19 | 34% | 2% | 45 | Search BRANCH+PREDICTION | Search BRANCH+PREDICTION |
2 | VALUE PREDICTION | 15 | 50% | 1% | 22 | Search VALUE+PREDICTION | Search VALUE+PREDICTION |
3 | THREAD LEVEL SPECULATION | 13 | 46% | 1% | 22 | Search THREAD+LEVEL+SPECULATION | Search THREAD+LEVEL+SPECULATION |
4 | SIMULTANEOUS MULTITHREADING | 12 | 39% | 1% | 25 | Search SIMULTANEOUS+MULTITHREADING | Search SIMULTANEOUS+MULTITHREADING |
5 | CACHE MEMORY | 12 | 24% | 2% | 42 | Search CACHE+MEMORY | Search CACHE+MEMORY |
6 | BRANCH TARGET BUFFER | 12 | 54% | 1% | 15 | Search BRANCH+TARGET+BUFFER | Search BRANCH+TARGET+BUFFER |
7 | RUNAHEAD EXECUTION | 9 | 83% | 0% | 5 | Search RUNAHEAD+EXECUTION | Search RUNAHEAD+EXECUTION |
8 | PREFETCHING | 7 | 15% | 2% | 45 | Search PREFETCHING | Search PREFETCHING |
9 | SPECULATIVE PARALLELIZATION | 7 | 42% | 1% | 13 | Search SPECULATIVE+PARALLELIZATION | Search SPECULATIVE+PARALLELIZATION |
10 | CACHE MEMORIES | 7 | 21% | 2% | 29 | Search CACHE+MEMORIES | Search CACHE+MEMORIES |
Key Words Plus |
Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|
1 | SYSTEM MICROARCHITECTURE | 7 | 53% | 0% | 9 |
2 | MICROPROCESSOR | 6 | 10% | 3% | 59 |
3 | BRANCH PREDICTION | 5 | 50% | 0% | 7 |
4 | LEAKAGE POWER | 4 | 31% | 1% | 12 |
5 | CONFIGURABLE CACHE | 4 | 75% | 0% | 3 |
6 | SMT PROCESSORS | 3 | 57% | 0% | 4 |
7 | CACHE MEMORY | 3 | 100% | 0% | 3 |
8 | CACHE | 3 | 10% | 2% | 30 |
9 | SHARED CACHES | 3 | 37% | 0% | 7 |
10 | PREDICATED EXECUTION | 3 | 60% | 0% | 3 |
Journals |
Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|
1 | ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION | 24 | 25% | 5% | 84 |
2 | IEEE MICRO | 19 | 12% | 8% | 145 |
3 | IEEE COMPUTER ARCHITECTURE LETTERS | 7 | 25% | 1% | 23 |
Reviews |
Title | Publ. year | Cit. | Active references |
% act. ref. to same field |
---|---|---|---|---|
A survey of processors with explicit multithreading | 2003 | 58 | 20 | 75% |
Simulation of computer architectures: Simulators, benchmarks, methodologies, and recommendations | 2006 | 22 | 20 | 80% |
Multithreaded processors | 2002 | 13 | 24 | 75% |
Decisive aspects in the evolution of microprocessors | 2004 | 7 | 33 | 52% |
USING CACHE PARTITIONING IN X.500 FOR FASTER NAME RESOLUTION IN X.400 | 1994 | 0 | 4 | 75% |
MICROPROCESSOR MEMORY MANAGEMENT UNITS | 1990 | 4 | 3 | 67% |
CACHE MEMORIES | 1982 | 129 | 6 | 17% |
INTEGRATION OF MACHINE ORGANIZATION AND CONTROL PROGRAM DESIGN - REVIEW AND DIRECTION | 1983 | 1 | 3 | 33% |
Address terms |
Rank | Address term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|
1 | ENGN MICROPROCESSOR SYST | 9 | 83% | 0.3% | 5 |
2 | COMP SYST SECT | 5 | 63% | 0.3% | 5 |
3 | MICROPROCESSOR DEV | 4 | 42% | 0.4% | 8 |
4 | ARTECS GRP | 3 | 38% | 0.3% | 6 |
5 | PROC ARCHITECTURE | 3 | 60% | 0.2% | 3 |
6 | PARALLEL SYST ARCHITECTURE | 2 | 67% | 0.1% | 2 |
7 | SCA LE COMP SOFTWARE | 2 | 67% | 0.1% | 2 |
8 | COMP ENGN DISCA | 2 | 22% | 0.4% | 7 |
9 | ALPHA DEV GRP | 1 | 38% | 0.2% | 3 |
10 | COMP ARCHITECTURE CALCM | 1 | 100% | 0.1% | 2 |
Related classes at same level (level 1) |
Rank | Relatedness score | Related classes |
---|---|---|
1 | 0.0000248850 | POWER CAPPING//ANALYTICAL PERFORMANCE MODELS//CONSERVATION CORE |
2 | 0.0000173897 | REGISTER ALLOCATION//INSTRUCTION SCHEDULING//INSTRUCTION LEVEL PARALLELISM |
3 | 0.0000133071 | SHARED MEMORY MULTIPROCESSORS//DISTRIBUTED SHARED MEMORY//CACHE COHERENCE |
4 | 0.0000117292 | TRACE SIGNAL SELECTION//SILICON DEBUG//REAL TIME TRACE |
5 | 0.0000115813 | TRANSACTIONAL MEMORY//CONTENTION MANAGEMENT//SOFTWARE TRANSACTIONAL MEMORY |
6 | 0.0000103155 | PARALLEL MEMORY//STORAGE SCHEMES//SUBWORD PARALLELISM |
7 | 0.0000103099 | PARALLELIZING COMPILERS//LOOP TRANSFORMATIONS//PARALLELIZING COMPILER |
8 | 0.0000075388 | SRAM//PROCESS VARIATION//POWER GATING |
9 | 0.0000072622 | WORMHOLE ROUTING//NETWORK ON CHIP//NETWORK ON CHIP NOC |
10 | 0.0000069334 | WORK STEALING//SOFTWARE TECHNOL PROGRAMMING LANGUAGES//SINGLE ASSIGNMENT C |