Class information for: |
Basic class information |
| ID | Publications | Average number of references |
Avg. shr. active ref. in WoS |
|---|---|---|---|
| 27561 | 186 | 21.7 | 26% |
Classes in level above (level 2) |
| ID, lev. above |
Publications | Label for level above |
|---|---|---|
| 1040 | 9640 | JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//SINGLE EVENT UPSET SEU |
Terms with highest relevance score |
| Rank | Term | Type of term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
|---|---|---|---|---|---|---|
| 1 | SYST LEVEL INTEGRAT GRP | Address | 3 | 60% | 2% | 3 |
| 2 | DYNAMIC PARTIAL RECONFIGURATION DPR | Author keyword | 2 | 50% | 2% | 3 |
| 3 | DYNAMICALLY PROGRAMMABLE GATE ARRAY | Author keyword | 1 | 100% | 1% | 2 |
| 4 | DYNAMICALLY RECONFIGURABLE ARCHITECTURE | Author keyword | 1 | 50% | 1% | 2 |
| 5 | EMBEDDED SYST ON CHIP GRP | Address | 1 | 100% | 1% | 2 |
| 6 | MULTI CONTEXT SWITCH | Author keyword | 1 | 100% | 1% | 2 |
| 7 | MULTIPLE VALUED THRESHOLD LOGIC | Author keyword | 1 | 100% | 1% | 2 |
| 8 | NON DESTRUCTIVE OPERATION | Author keyword | 1 | 100% | 1% | 2 |
| 9 | INCREMENTAL ROUTING | Author keyword | 1 | 40% | 1% | 2 |
| 10 | FPGA SOFTWARE CORE GRP | Address | 1 | 33% | 1% | 2 |
Web of Science journal categories |
Author Key Words |
Key Words Plus |
| Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
|---|---|---|---|---|---|
| 1 | LOGIC BLOCKS | 4 | 50% | 3% | 6 |
| 2 | FPGA LOGIC BLOCKS | 3 | 57% | 2% | 4 |
| 3 | INTERCONNECT FAULTS | 1 | 50% | 1% | 2 |
| 4 | BIST ARCHITECTURE | 1 | 33% | 2% | 3 |
| 5 | LUT BASED FPGAS | 1 | 50% | 1% | 1 |
| 6 | VIRTEX 5 FPGAS | 1 | 50% | 1% | 1 |
| 7 | LOGIC ARRAYS | 0 | 33% | 1% | 1 |
| 8 | TOLERANT PROCESSOR ARRAYS | 0 | 33% | 1% | 1 |
| 9 | VLSI ARRAYS | 0 | 17% | 1% | 2 |
| 10 | OXIDE DEGRADATION | 0 | 25% | 1% | 1 |
Journals |
Reviews |
Address terms |
| Rank | Address term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
|---|---|---|---|---|---|
| 1 | SYST LEVEL INTEGRAT GRP | 3 | 60% | 1.6% | 3 |
| 2 | EMBEDDED SYST ON CHIP GRP | 1 | 100% | 1.1% | 2 |
| 3 | FPGA SOFTWARE CORE GRP | 1 | 33% | 1.1% | 2 |
| 4 | DESIGN AUTOMAT TEST | 1 | 50% | 0.5% | 1 |
| 5 | ELECT COMP SCI IMAGE | 1 | 50% | 0.5% | 1 |
| 6 | RELIABIL COMP | 1 | 50% | 0.5% | 1 |
| 7 | FAK ELEKTROTEHNIKO RACUNALNISTVO INFORMAT | 0 | 33% | 0.5% | 1 |
| 8 | FO T POST PROGRAMME | 0 | 33% | 0.5% | 1 |
| 9 | MED RUMENTAT ENGN | 0 | 33% | 0.5% | 1 |
| 10 | COMP SCI ENGN ITEC | 0 | 25% | 0.5% | 1 |
Related classes at same level (level 1) |
| Rank | Relatedness score | Related classes |
|---|---|---|
| 1 | 0.0000210097 | UNIDIRECTIONAL ERRORS//SELF CHECKING CIRCUITS//BALANCED CODES |
| 2 | 0.0000187877 | RECONFIGURABLE COMPUTING//INSTRUCTION SET EXTENSION ISE//ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS |
| 3 | 0.0000158585 | LOG SYST//EVOLVABLE HARDWARE//SELF REPLICATION |
| 4 | 0.0000138924 | COUNCILS OF GOVERNMENTS//LILLIAN WALD//SLUM CLEARANCE |
| 5 | 0.0000127053 | XRAY PHYS IMAGING//DISCRETE IMAGE PROCESSING//POSITIVITY PROBLEM |
| 6 | 0.0000121065 | FLOORPLANNING//PHYSICAL DESIGN//PLACEMENT |
| 7 | 0.0000115660 | NEUROMORPHIC NETWORKS//ELECTRONIC NANOTECHNOLOGY//CMOL |
| 8 | 0.0000098757 | BUILT IN REDUNDANCY ANALYSIS BIRA//CATASTROPHIC FAULT PATTERNS//CRITICAL AREA |
| 9 | 0.0000098198 | CREPING//CORE CENTRIC//SPECIAL PURPOSE PROCESSOR |
| 10 | 0.0000088906 | LABEL EQUIVALENCE//LABELING ALGORITHM//FIRST SCAN |