Class information for:
Level 1: ITERATIVE LOGIC ARRAYS//C TESTABILITY//CELL FAULT MODEL

Basic class information
ID Publications Average number
of references		 Avg. shr. active
ref. in WoS
19778 426 18.2 25%


Bar chart of Publication_year

Last years might be incomplete

Classes in level above (level 2)


ID, lev.
above		 Publications Label for level above
1040 9640 JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//SINGLE EVENT UPSET SEU

Terms with highest relevance score


Rank Term Type of term Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class
1 ITERATIVE LOGIC ARRAYS Author keyword 21 90% 2% 9
2 C TESTABILITY Author keyword 10 63% 2% 10
3 CELL FAULT MODEL Author keyword 6 71% 1% 5
4 REGULAR CIRCUITS Author keyword 3 100% 1% 3
5 STUCK OPEN FAULTS Author keyword 2 44% 1% 4
6 ITERATIVE LOGIC ARRAY Author keyword 2 36% 1% 5
7 LINEAR TESTABILITY Author keyword 2 67% 0% 2
8 SWITCH LEVEL MODELING Author keyword 2 67% 0% 2
9 AMBITUS Author keyword 1 100% 0% 2
10 CMOS TRANSISTOR NETWORKS Author keyword 1 100% 0% 2

Web of Science journal categories

Author Key Words


Rank Web of Science journal category Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class		 LCSH search Wikipedia search
1 ITERATIVE LOGIC ARRAYS 21 90% 2% 9 Search ITERATIVE+LOGIC+ARRAYS Search ITERATIVE+LOGIC+ARRAYS
2 C TESTABILITY 10 63% 2% 10 Search C+TESTABILITY Search C+TESTABILITY
3 CELL FAULT MODEL 6 71% 1% 5 Search CELL+FAULT+MODEL Search CELL+FAULT+MODEL
4 REGULAR CIRCUITS 3 100% 1% 3 Search REGULAR+CIRCUITS Search REGULAR+CIRCUITS
5 STUCK OPEN FAULTS 2 44% 1% 4 Search STUCK+OPEN+FAULTS Search STUCK+OPEN+FAULTS
6 ITERATIVE LOGIC ARRAY 2 36% 1% 5 Search ITERATIVE+LOGIC+ARRAY Search ITERATIVE+LOGIC+ARRAY
7 LINEAR TESTABILITY 2 67% 0% 2 Search LINEAR+TESTABILITY Search LINEAR+TESTABILITY
8 SWITCH LEVEL MODELING 2 67% 0% 2 Search SWITCH+LEVEL+MODELING Search SWITCH+LEVEL+MODELING
9 AMBITUS 1 100% 0% 2 Search AMBITUS Search AMBITUS
10 CMOS TRANSISTOR NETWORKS 1 100% 0% 2 Search CMOS+TRANSISTOR+NETWORKS Search CMOS+TRANSISTOR+NETWORKS

Key Words Plus


Rank Web of Science journal category Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class
1 ITERATIVE LOGIC ARRAYS 12 50% 4% 17
2 TESTABILITY 3 10% 6% 24
3 PLA DESIGN 2 67% 0% 2
4 COMBINATIONAL LOGIC CIRCUITS 2 19% 2% 8
5 COMBINATIONAL CELLS 1 100% 0% 2
6 MODIFIED BOOTH MULTIPLIERS 1 50% 0% 2
7 STUCK OPEN FAULTS 1 100% 0% 2
8 PROGRAMMABLE LOGIC ARRAYS 1 24% 1% 4
9 MOS INTEGRATED CIRCUITS 1 19% 1% 5
10 TESTABLE DESIGN 1 27% 1% 3

Journals

Reviews


Title Publ. year Cit. Active
references		 % act. ref.
to same field
CIRCUIT ANALYSIS, LOGIC SIMULATION, AND DESIGN VERIFICATION FOR VLSI 1983 22 15 27%

Address terms


Rank Address term Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ.
in class
1 TEST TECHNOL GRP 1 50% 0.2% 1
2 INGN ELETTR GESTIONALE MECCAN 0 33% 0.2% 1
3 SOMERSET POWERPC DESIGN 0 20% 0.2% 1
4 CNR CENS ITALIAN COUNCIL 0 100% 0.2% 1
5 CNR E ORAZIONE NUMERALE SEGNALI 0 100% 0.2% 1
6 PROCESSOR DESIGN 0 100% 0.2% 1

Related classes at same level (level 1)


Rank Relatedness score Related classes
1 0.0000213440 TRANSITION FAULTS//FUNCTIONAL BROADSIDE TESTS//JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
2 0.0000172078 UNIDIRECTIONAL ERRORS//SELF CHECKING CIRCUITS//BALANCED CODES
3 0.0000162703 SHORT CIRCUIT POWER DISSIPATION//TRANSISTOR SIZING//GATE SIZING
4 0.0000128712 TIME WARP//DISTRIBUTED SIMULATION//OPTIMISTIC SYNCHRONIZATION
5 0.0000125355 REED MULLER EXPANSIONS//FRENCH SING ORE//REED MULLER EXPANSION
6 0.0000112682 STATE ASSIGNMENT//FSM SYNTHESIS//LOGIC SYNTHESIS
7 0.0000099829 JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS//ANALOG FAULT DIAGNOSIS//LOOPBACK TEST
8 0.0000090414 BUILT IN REDUNDANCY ANALYSIS BIRA//CATASTROPHIC FAULT PATTERNS//CRITICAL AREA
9 0.0000081211 PASS TRANSISTOR LOGIC//DIGITAL ARITHMETIC//FIXED WIDTH MULTIPLIER
10 0.0000078126 READ ONCE BRANCHING PROGRAMS//ORDERED BINARY DECISION DIAGRAMS//INFORMAT LS2