Class information for:
Level 1: SHORT CIRCUIT POWER DISSIPATION//TRANSISTOR SIZING//GATE SIZING

Basic class information
ID Publications Average number
of references		 Avg. shr. active
ref. in WoS
19665 430 17.4 38%


Bar chart of Publication_year

Last years might be incomplete

Classes in level above (level 2)


ID, lev.
above		 Publications Label for level above
923 10486 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//HIGH LEVEL SYNTHESIS

Terms with highest relevance score


Rank Term Type of term Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class
1 SHORT CIRCUIT POWER DISSIPATION Author keyword 9 83% 1% 5
2 TRANSISTOR SIZING Author keyword 9 34% 5% 21
3 GATE SIZING Author keyword 8 29% 5% 22
4 COLUMN DECODER Author keyword 4 75% 1% 3
5 POST LAYOUT OPTIMIZATION Author keyword 4 75% 1% 3
6 CMOS BUFFER Author keyword 4 56% 1% 5
7 DISCRETE GATE SIZING Author keyword 3 100% 1% 3
8 CMOS GATES Author keyword 3 40% 1% 6
9 ALPHA POWER LAW Author keyword 2 67% 0% 2
10 SENSITIZABLE PATH Author keyword 2 67% 0% 2

Web of Science journal categories

Author Key Words


Rank Web of Science journal category Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class		 LCSH search Wikipedia search
1 SHORT CIRCUIT POWER DISSIPATION 9 83% 1% 5 Search SHORT+CIRCUIT+POWER+DISSIPATION Search SHORT+CIRCUIT+POWER+DISSIPATION
2 TRANSISTOR SIZING 9 34% 5% 21 Search TRANSISTOR+SIZING Search TRANSISTOR+SIZING
3 GATE SIZING 8 29% 5% 22 Search GATE+SIZING Search GATE+SIZING
4 COLUMN DECODER 4 75% 1% 3 Search COLUMN+DECODER Search COLUMN+DECODER
5 POST LAYOUT OPTIMIZATION 4 75% 1% 3 Search POST+LAYOUT+OPTIMIZATION Search POST+LAYOUT+OPTIMIZATION
6 CMOS BUFFER 4 56% 1% 5 Search CMOS+BUFFER Search CMOS+BUFFER
7 DISCRETE GATE SIZING 3 100% 1% 3 Search DISCRETE+GATE+SIZING Search DISCRETE+GATE+SIZING
8 CMOS GATES 3 40% 1% 6 Search CMOS+GATES Search CMOS+GATES
9 ALPHA POWER LAW 2 67% 0% 2 Search ALPHA+POWER+LAW Search ALPHA+POWER+LAW
10 SENSITIZABLE PATH 2 67% 0% 2 Search SENSITIZABLE+PATH Search SENSITIZABLE+PATH

Key Words Plus


Rank Web of Science journal category Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class
1 INVERTER DELAY 19 76% 3% 13
2 CMOS INVERTER DELAY 8 56% 2% 10
3 PROPAGATION DELAY 2 20% 2% 10
4 EFFORT MODEL 2 67% 0% 2
5 SIMULTANEOUS GATE 2 43% 1% 3
6 TAPERED BUFFER 2 43% 1% 3
7 MOSFET MODEL 2 12% 3% 12
8 DELAY EVALUATION 1 33% 1% 3
9 TRANSISTOR SIZING PROBLEM 1 40% 0% 2
10 SUBMICRON CMOS 1 16% 1% 5

Journals

Reviews

Address terms


Rank Address term Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ.
in class
1 NANOMETER DESIGN 1 100% 0.5% 2
2 ADV TOOLS 1 50% 0.2% 1
3 CIRCUIT SIMULAT GRP 1 50% 0.2% 1
4 DESIGN ENABLEMENT SERV 1 50% 0.2% 1
5 DIGITAL VIDEO TECHNOL 1 50% 0.2% 1
6 WIRELESS INFRASTRUCT BRANCH 1 50% 0.2% 1
7 INFORMAT PPGC PGMICRO 0 33% 0.2% 1
8 EDIFICIO CICA 0 18% 0.5% 2
9 INTEGRATED SYST DESIGN 0 25% 0.2% 1
10 LIRMM UMR 5506 0 25% 0.2% 1

Related classes at same level (level 1)


Rank Relatedness score Related classes
1 0.0000225662 SRAM//PROCESS VARIATION//POWER GATING
2 0.0000189987 INTERCONNECT MODELING//MOMENT MATCHING TECHNIQUES//HIGH SPEED INTERCONNECTS
3 0.0000181370 CLOCK TREE//CLOCK SKEW//CLOCK DISTRIBUTION
4 0.0000162703 ITERATIVE LOGIC ARRAYS//C TESTABILITY//CELL FAULT MODEL
5 0.0000159682 POWER ESTIMATION//SWITCHING ACTIVITY//BUS ENCODING
6 0.0000139644 PASS TRANSISTOR LOGIC//DIGITAL ARITHMETIC//FIXED WIDTH MULTIPLIER
7 0.0000111235 SUBSTRATE NOISE//SUBSTRATE COUPLING//POWER SUPPLY NOISE
8 0.0000102803 NONQUASI STATIC NQS EFFECT//QUCS//RSCE
9 0.0000096182 PASSIVATED CONTACT//POLYSILICON EMITTER//CLOCK ACCESS TIME
10 0.0000089364 BALLISTIC MOBILITY//HIGH ELECTRIC FIELD TRANSPORT//TRANSIT TIME DELAY