Class information for: |
Basic class information |
ID | Publications | Average number of references |
Avg. shr. active ref. in WoS |
---|---|---|---|
14591 | 694 | 20.7 | 28% |
Classes in level above (level 2) |
ID, lev. above |
Publications | Label for level above |
---|---|---|
923 | 10486 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//HIGH LEVEL SYNTHESIS |
Terms with highest relevance score |
Rank | Term | Type of term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|---|
1 | POWER ESTIMATION | Author keyword | 23 | 28% | 10% | 69 |
2 | SWITCHING ACTIVITY | Author keyword | 12 | 28% | 5% | 37 |
3 | BUS ENCODING | Author keyword | 7 | 40% | 2% | 14 |
4 | VECTOR COMPACTION | Author keyword | 6 | 71% | 1% | 5 |
5 | BUS INVERT CODING | Author keyword | 5 | 60% | 1% | 6 |
6 | TRANSITION ACTIVITY | Author keyword | 5 | 63% | 1% | 5 |
7 | BUS INVERT | Author keyword | 4 | 67% | 1% | 4 |
8 | SOURCE CODE TRANSFORMATIONS | Author keyword | 3 | 100% | 0% | 3 |
9 | POWER MODELING AND ESTIMATION | Author keyword | 2 | 36% | 1% | 5 |
10 | ACHIEVABLE BOUNDS | Author keyword | 2 | 67% | 0% | 2 |
Web of Science journal categories |
Author Key Words |
Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
LCSH search | Wikipedia search |
---|---|---|---|---|---|---|---|
1 | POWER ESTIMATION | 23 | 28% | 10% | 69 | Search POWER+ESTIMATION | Search POWER+ESTIMATION |
2 | SWITCHING ACTIVITY | 12 | 28% | 5% | 37 | Search SWITCHING+ACTIVITY | Search SWITCHING+ACTIVITY |
3 | BUS ENCODING | 7 | 40% | 2% | 14 | Search BUS+ENCODING | Search BUS+ENCODING |
4 | VECTOR COMPACTION | 6 | 71% | 1% | 5 | Search VECTOR+COMPACTION | Search VECTOR+COMPACTION |
5 | BUS INVERT CODING | 5 | 60% | 1% | 6 | Search BUS+INVERT+CODING | Search BUS+INVERT+CODING |
6 | TRANSITION ACTIVITY | 5 | 63% | 1% | 5 | Search TRANSITION+ACTIVITY | Search TRANSITION+ACTIVITY |
7 | BUS INVERT | 4 | 67% | 1% | 4 | Search BUS+INVERT | Search BUS+INVERT |
8 | SOURCE CODE TRANSFORMATIONS | 3 | 100% | 0% | 3 | Search SOURCE+CODE+TRANSFORMATIONS | Search SOURCE+CODE+TRANSFORMATIONS |
9 | POWER MODELING AND ESTIMATION | 2 | 36% | 1% | 5 | Search POWER+MODELING+AND+ESTIMATION | Search POWER+MODELING+AND+ESTIMATION |
10 | ACHIEVABLE BOUNDS | 2 | 67% | 0% | 2 | Search ACHIEVABLE+BOUNDS | Search ACHIEVABLE+BOUNDS |
Key Words Plus |
Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|
1 | BUSSES | 17 | 75% | 2% | 12 |
2 | PROBABILISTIC SIMULATION | 6 | 53% | 1% | 8 |
3 | POWER ESTIMATION | 3 | 29% | 1% | 10 |
4 | SWITCHING ACTIVITY | 3 | 26% | 1% | 9 |
5 | INVERT | 2 | 67% | 0% | 2 |
6 | TRANSITION ACTIVITY | 2 | 50% | 0% | 3 |
7 | ERROR DETECTION CODES | 1 | 40% | 0% | 2 |
8 | SAVING POWER | 1 | 40% | 0% | 2 |
9 | RTL | 1 | 22% | 1% | 4 |
10 | MULTIPROCESSOR SOC | 1 | 23% | 0% | 3 |
Journals |
Reviews |
Title | Publ. year | Cit. | Active references |
% act. ref. to same field |
---|---|---|---|---|
High-level power modeling, estimation, and optimization | 1998 | 75 | 22 | 68% |
System-level power optimization: Techniques and tools | 2000 | 121 | 53 | 32% |
Power analysis and estimation for SOC design: Techniques and tools | 2004 | 0 | 1 | 100% |
Overview of power/energy consumption analysis and optimization tools in SOCS | 2004 | 0 | 14 | 50% |
Low power VLSI design techniques - The current state | 1998 | 0 | 15 | 60% |
POWER CONSCIOUS CAD TOOLS AND METHODOLOGIES - A PERSPECTIVE | 1995 | 74 | 12 | 17% |
Address terms |
Rank | Address term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|
1 | EMBEDDED COMP SCI | 2 | 67% | 0.3% | 2 |
2 | BUSINESS LINE IDENTIFICAT | 1 | 100% | 0.3% | 2 |
3 | SYST CIRCUIT DESIGN | 1 | 100% | 0.3% | 2 |
4 | EMBEDDED COMP SYST | 1 | 11% | 1.4% | 10 |
5 | BRAINKOREA 21 | 1 | 50% | 0.1% | 1 |
6 | CAIRN TEAM | 1 | 50% | 0.1% | 1 |
7 | ENSSAT ENGN | 1 | 50% | 0.1% | 1 |
8 | FUNDAMENTAL EXPT ELECT PHYS SYST | 1 | 50% | 0.1% | 1 |
9 | HIGH SPEED MIXED SIGNAL | 1 | 50% | 0.1% | 1 |
10 | LOW POWER DESIGN | 1 | 50% | 0.1% | 1 |
Related classes at same level (level 1) |
Rank | Relatedness score | Related classes |
---|---|---|
1 | 0.0000174948 | HIGH LEVEL SYNTHESIS//BEHAVIORAL SYNTHESIS//MODULE SELECTION |
2 | 0.0000159682 | SHORT CIRCUIT POWER DISSIPATION//TRANSISTOR SIZING//GATE SIZING |
3 | 0.0000135810 | SRAM//PROCESS VARIATION//POWER GATING |
4 | 0.0000132528 | BITWIDTH//WORD LENGTH OPTIMIZATION//BIT WIDTH ALLOCATION |
5 | 0.0000128326 | STATE ASSIGNMENT//FSM SYNTHESIS//LOGIC SYNTHESIS |
6 | 0.0000120878 | CLOCK TREE//CLOCK SKEW//CLOCK DISTRIBUTION |
7 | 0.0000090376 | SLEEP MODE//POWER SAVING//SLEEP INTERVAL |
8 | 0.0000088515 | CODE TRANSFORMATIONS//DUAL RING USAGE//SIMPLIFIED PROTOCOL |
9 | 0.0000078136 | ADIABATIC CIRCUIT//ADIABATIC CHARGING//ENERGY RECOVERY LOGIC |
10 | 0.0000074215 | STREAMIT//SYNCHRONOUS DATAFLOW//DESIGN AUTOMATION FOR EMBEDDED SYSTEMS |