Class information for: |
Basic class information |
| ID | Publications | Average number of references |
Avg. shr. active ref. in WoS |
|---|---|---|---|
| 14410 | 705 | 18.9 | 39% |
Classes in level above (level 2) |
| ID, lev. above |
Publications | Label for level above |
|---|---|---|
| 923 | 10486 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//HIGH LEVEL SYNTHESIS |
Terms with highest relevance score |
| Rank | Term | Type of term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
|---|---|---|---|---|---|---|
| 1 | CLOCK TREE | Author keyword | 20 | 49% | 4% | 29 |
| 2 | CLOCK SKEW | Author keyword | 16 | 29% | 7% | 48 |
| 3 | CLOCK DISTRIBUTION | Author keyword | 15 | 31% | 6% | 40 |
| 4 | SEMI SYNCHRONOUS CIRCUIT | Author keyword | 14 | 100% | 1% | 7 |
| 5 | CLOCK TREE SYNTHESIS | Author keyword | 12 | 54% | 2% | 15 |
| 6 | CLOCK SCHEDULING | Author keyword | 9 | 55% | 2% | 11 |
| 7 | CLOCK SKEW SCHEDULING | Author keyword | 8 | 56% | 1% | 10 |
| 8 | RETIMING | Author keyword | 8 | 22% | 5% | 32 |
| 9 | FLIP FLOPS | Author keyword | 8 | 23% | 4% | 29 |
| 10 | CLOCK ROUTING | Author keyword | 7 | 50% | 1% | 10 |
Web of Science journal categories |
Author Key Words |
| Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
LCSH search | Wikipedia search |
|---|---|---|---|---|---|---|---|
| 1 | CLOCK TREE | 20 | 49% | 4% | 29 | Search CLOCK+TREE | Search CLOCK+TREE |
| 2 | CLOCK SKEW | 16 | 29% | 7% | 48 | Search CLOCK+SKEW | Search CLOCK+SKEW |
| 3 | CLOCK DISTRIBUTION | 15 | 31% | 6% | 40 | Search CLOCK+DISTRIBUTION | Search CLOCK+DISTRIBUTION |
| 4 | SEMI SYNCHRONOUS CIRCUIT | 14 | 100% | 1% | 7 | Search SEMI+SYNCHRONOUS+CIRCUIT | Search SEMI+SYNCHRONOUS+CIRCUIT |
| 5 | CLOCK TREE SYNTHESIS | 12 | 54% | 2% | 15 | Search CLOCK+TREE+SYNTHESIS | Search CLOCK+TREE+SYNTHESIS |
| 6 | CLOCK SCHEDULING | 9 | 55% | 2% | 11 | Search CLOCK+SCHEDULING | Search CLOCK+SCHEDULING |
| 7 | CLOCK SKEW SCHEDULING | 8 | 56% | 1% | 10 | Search CLOCK+SKEW+SCHEDULING | Search CLOCK+SKEW+SCHEDULING |
| 8 | RETIMING | 8 | 22% | 5% | 32 | Search RETIMING | Search RETIMING |
| 9 | FLIP FLOPS | 8 | 23% | 4% | 29 | Search FLIP+FLOPS | Search FLIP+FLOPS |
| 10 | CLOCK ROUTING | 7 | 50% | 1% | 10 | Search CLOCK+ROUTING | Search CLOCK+ROUTING |
Key Words Plus |
| Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
|---|---|---|---|---|---|
| 1 | DELAY AREA DOMAIN | 12 | 86% | 1% | 6 |
| 2 | CLOCKED STORAGE ELEMENTS | 6 | 100% | 1% | 4 |
| 3 | LATCHES | 5 | 34% | 2% | 12 |
| 4 | IMPROVED SPEED | 4 | 75% | 0% | 3 |
| 5 | LEVEL CLOCKED CIRCUITS | 4 | 75% | 0% | 3 |
| 6 | RISC MICROPROCESSOR | 4 | 36% | 1% | 9 |
| 7 | LOW POWER SYSTEMS | 4 | 46% | 1% | 6 |
| 8 | CLOCK CMOS LATCHES | 3 | 100% | 0% | 3 |
| 9 | SKEW OPTIMIZATION | 3 | 60% | 0% | 3 |
| 10 | SKEW | 3 | 10% | 3% | 24 |
Journals |
Reviews |
| Title | Publ. year | Cit. | Active references |
% act. ref. to same field |
|---|---|---|---|---|
| Clock distribution networks in synchronous digital integrated circuits | 2001 | 156 | 61 | 52% |
Address terms |
| Rank | Address term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
|---|---|---|---|---|---|
| 1 | INTEGRATED CIRCUIT DESIGN EMBEDDED SYST | 3 | 100% | 0.4% | 3 |
| 2 | NICS GRP | 3 | 100% | 0.4% | 3 |
| 3 | GLOBAL INFORMAT TECHNOL | 2 | 67% | 0.3% | 2 |
| 4 | DIEES DIPARTIMENTO INGN ELETTR ELETTRON SISTEMI | 1 | 50% | 0.1% | 1 |
| 5 | EECS ELECT ENGN COMP SCI | 1 | 50% | 0.1% | 1 |
| 6 | ELE ENGN COMP SCI | 1 | 50% | 0.1% | 1 |
| 7 | IESIA | 1 | 50% | 0.1% | 1 |
| 8 | INFORM COMM ENG | 1 | 50% | 0.1% | 1 |
| 9 | ISRAEL DESIGN | 1 | 50% | 0.1% | 1 |
| 10 | LOG SYNTH GRP | 1 | 50% | 0.1% | 1 |
Related classes at same level (level 1) |
| Rank | Relatedness score | Related classes |
|---|---|---|
| 1 | 0.0000192220 | ADIABATIC CIRCUIT//ADIABATIC CHARGING//ENERGY RECOVERY LOGIC |
| 2 | 0.0000181370 | SHORT CIRCUIT POWER DISSIPATION//TRANSISTOR SIZING//GATE SIZING |
| 3 | 0.0000166755 | SRAM//PROCESS VARIATION//POWER GATING |
| 4 | 0.0000149933 | ASYNCHRONOUS CIRCUITS//SIGNAL TRANSITION GRAPH//SIGNAL TRANSITION GRAPHS |
| 5 | 0.0000149439 | PASS TRANSISTOR LOGIC//DIGITAL ARITHMETIC//FIXED WIDTH MULTIPLIER |
| 6 | 0.0000122428 | SUBSTRATE NOISE//SUBSTRATE COUPLING//POWER SUPPLY NOISE |
| 7 | 0.0000120878 | POWER ESTIMATION//SWITCHING ACTIVITY//BUS ENCODING |
| 8 | 0.0000115127 | HIGH LEVEL SYNTHESIS//BEHAVIORAL SYNTHESIS//MODULE SELECTION |
| 9 | 0.0000111714 | INTERCONNECT MODELING//MOMENT MATCHING TECHNIQUES//HIGH SPEED INTERCONNECTS |
| 10 | 0.0000077308 | IBM SYST TECHNOL GRP//390//SERVER GRP |