Class information for: |
Basic class information |
ID | Publications | Average number of references |
Avg. shr. active ref. in WoS |
---|---|---|---|
13773 | 751 | 27.3 | 25% |
Classes in level above (level 2) |
ID, lev. above |
Publications | Label for level above |
---|---|---|
923 | 10486 | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//HIGH LEVEL SYNTHESIS |
Terms with highest relevance score |
Rank | Term | Type of term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|---|
1 | STREAMIT | Author keyword | 9 | 67% | 1% | 8 |
2 | SYNCHRONOUS DATAFLOW | Author keyword | 8 | 45% | 2% | 13 |
3 | DESIGN AUTOMATION FOR EMBEDDED SYSTEMS | Journal | 6 | 15% | 5% | 38 |
4 | ACTOR ORIENTED DESIGN | Author keyword | 6 | 100% | 1% | 4 |
5 | SYST LEVEL SYNTH GRP | Address | 4 | 67% | 1% | 4 |
6 | DATAFLOW PROCESS NETWORK | Author keyword | 4 | 75% | 0% | 3 |
7 | QUASI STATIC SCHEDULING | Author keyword | 4 | 56% | 1% | 5 |
8 | DATAFLOW PROGRAMMING | Author keyword | 4 | 32% | 1% | 10 |
9 | SYNCHRONOUS DATA FLOW | Author keyword | 4 | 41% | 1% | 7 |
10 | BLOCK DIAGRAM COMPILER | Author keyword | 3 | 100% | 0% | 3 |
Web of Science journal categories |
Author Key Words |
Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
LCSH search | Wikipedia search |
---|---|---|---|---|---|---|---|
1 | STREAMIT | 9 | 67% | 1% | 8 | Search STREAMIT | Search STREAMIT |
2 | SYNCHRONOUS DATAFLOW | 8 | 45% | 2% | 13 | Search SYNCHRONOUS+DATAFLOW | Search SYNCHRONOUS+DATAFLOW |
3 | ACTOR ORIENTED DESIGN | 6 | 100% | 1% | 4 | Search ACTOR+ORIENTED+DESIGN | Search ACTOR+ORIENTED+DESIGN |
4 | DATAFLOW PROCESS NETWORK | 4 | 75% | 0% | 3 | Search DATAFLOW+PROCESS+NETWORK | Search DATAFLOW+PROCESS+NETWORK |
5 | QUASI STATIC SCHEDULING | 4 | 56% | 1% | 5 | Search QUASI+STATIC+SCHEDULING | Search QUASI+STATIC+SCHEDULING |
6 | DATAFLOW PROGRAMMING | 4 | 32% | 1% | 10 | Search DATAFLOW+PROGRAMMING | Search DATAFLOW+PROGRAMMING |
7 | SYNCHRONOUS DATA FLOW | 4 | 41% | 1% | 7 | Search SYNCHRONOUS+DATA+FLOW | Search SYNCHRONOUS+DATA+FLOW |
8 | BLOCK DIAGRAM COMPILER | 3 | 100% | 0% | 3 | Search BLOCK+DIAGRAM+COMPILER | Search BLOCK+DIAGRAM+COMPILER |
9 | REPETITIVE STRUCTURE MODELING | 3 | 100% | 0% | 3 | Search REPETITIVE+STRUCTURE+MODELING | Search REPETITIVE+STRUCTURE+MODELING |
10 | DATAFLOW GRAPHS | 3 | 37% | 1% | 7 | Search DATAFLOW+GRAPHS | Search DATAFLOW+GRAPHS |
Key Words Plus |
Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|
1 | SYNCHRONOUS DATA FLOW | 48 | 52% | 9% | 66 |
2 | DATA FLOW | 14 | 28% | 6% | 42 |
3 | SOFTWARE SYNTHESIS | 6 | 80% | 1% | 4 |
4 | DATA FLOW PROGRAMS | 5 | 42% | 1% | 10 |
5 | MULTIPROCESSOR SOC | 2 | 38% | 1% | 5 |
6 | CHIP HETEROGENEOUS MULTIPROCESSORS | 2 | 67% | 0% | 2 |
7 | HETEROGENEOUS ARCHITECTURES | 2 | 67% | 0% | 2 |
8 | ITERATION PERIOD | 2 | 67% | 0% | 2 |
9 | TRANSACTION LEVEL | 2 | 67% | 0% | 2 |
10 | DESIGN FLOW | 2 | 36% | 1% | 4 |
Journals |
Rank | Web of Science journal category | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|
1 | DESIGN AUTOMATION FOR EMBEDDED SYSTEMS | 6 | 15% | 5% | 38 |
Reviews |
Title | Publ. year | Cit. | Active references |
% act. ref. to same field |
---|---|---|---|---|
Methods for evaluating and covering the design space during early design development | 2004 | 68 | 26 | 27% |
SETI@home, BOINC, and Volunteer Distributed Computing | 2012 | 8 | 8 | 13% |
Design of embedded systems: Formal models, validation, and synthesis | 1997 | 135 | 16 | 13% |
Toward the tools selection in model based system engineering for embedded systems-A systematic literature review | 2015 | 0 | 20 | 30% |
Algorithm/Architecture Co-Exploration of Visual Computing on Emergent Platforms: Overview and Future Prospects | 2009 | 8 | 45 | 7% |
A survey of stream processing | 1997 | 96 | 38 | 3% |
Address terms |
Rank | Address term | Relevance score (tfidf) |
Class's shr. of term's tot. occurrences |
Shr. of publ. in class containing term |
Num. of publ. in class |
---|---|---|---|---|---|
1 | SYST LEVEL SYNTH GRP | 4 | 67% | 0.5% | 4 |
2 | FERMAT | 3 | 50% | 0.5% | 4 |
3 | CODESIGN PARALLEL PROC | 2 | 67% | 0.3% | 2 |
4 | COMP ARCHITECTU EMBEDDED SYST GRP | 2 | 67% | 0.3% | 2 |
5 | MULTIMEDIA ARCHITECTU GRP | 2 | 67% | 0.3% | 2 |
6 | SCI STI MM | 2 | 67% | 0.3% | 2 |
7 | INFORMAT TECHNOL SYST ELECT ENGN | 1 | 100% | 0.3% | 2 |
8 | OSTRE | 1 | 100% | 0.3% | 2 |
9 | PROGRAMMABLE SYST | 1 | 50% | 0.3% | 2 |
10 | TEISA DPT | 1 | 100% | 0.3% | 2 |
Related classes at same level (level 1) |
Rank | Relatedness score | Related classes |
---|---|---|
1 | 0.0000251414 | HARDWARE SOFTWARE PARTITIONING//HARDWARE SOFTWARE COSYNTHESIS//PROCESSOR SYNTHESIS |
2 | 0.0000192380 | SYNCHRONOUS LANGUAGES//STATECHARTS//ESTEREL |
3 | 0.0000163704 | HIGH LEVEL SYNTHESIS//BEHAVIORAL SYNTHESIS//MODULE SELECTION |
4 | 0.0000116483 | RECONFIGURABLE COMPUTING//INSTRUCTION SET EXTENSION ISE//ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS |
5 | 0.0000102233 | OPEN SOURCE OS//COMP ENGN COMP COMMUN//BOOTING TIME |
6 | 0.0000101550 | WORMHOLE ROUTING//NETWORK ON CHIP//NETWORK ON CHIP NOC |
7 | 0.0000091360 | BITWIDTH//WORD LENGTH OPTIMIZATION//BIT WIDTH ALLOCATION |
8 | 0.0000080909 | LAYERED QUEUEING NETWORKS//SOFTWARE PERFORMANCE ENGINEERING//LAYERED QUEUING NETWORKS |
9 | 0.0000076987 | REAL-TIME SYSTEMS//SCHEDULABILITY ANALYSIS//REAL TIME SYSTEMS |
10 | 0.0000074215 | POWER ESTIMATION//SWITCHING ACTIVITY//BUS ENCODING |