Class information for:
Level 1: HIGH LEVEL SYNTHESIS//BEHAVIORAL SYNTHESIS//MODULE SELECTION

Basic class information
ID Publications Average number
of references		 Avg. shr. active
ref. in WoS
12877 813 22.7 24%


Bar chart of Publication_year

Last years might be incomplete

Classes in level above (level 2)


ID, lev.
above		 Publications Label for level above
923 10486 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS//IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//HIGH LEVEL SYNTHESIS

Terms with highest relevance score


Rank Term Type of term Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class
1 HIGH LEVEL SYNTHESIS Author keyword 43 24% 19% 157
2 BEHAVIORAL SYNTHESIS Author keyword 11 35% 3% 26
3 MODULE SELECTION Author keyword 9 59% 1% 10
4 MULTIPLE VOLTAGES Author keyword 5 63% 1% 5
5 MULTIPLE VOLTAGE SCHEDULING Author keyword 4 75% 0% 3
6 HIGH LEVEL SYNTHESIS HLS Author keyword 4 35% 1% 9
7 DATA PATH SYNTHESIS Author keyword 4 41% 1% 7
8 FAULT SECURITY Author keyword 3 57% 0% 4
9 CONTROL FLOW INTENSIVE BEHAVIORS Author keyword 3 100% 0% 3
10 DYNAMIC FREQUENCY CLOCKING Author keyword 3 100% 0% 3

Web of Science journal categories

Author Key Words


Rank Web of Science journal category Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class		 LCSH search Wikipedia search
1 HIGH LEVEL SYNTHESIS 43 24% 19% 157 Search HIGH+LEVEL+SYNTHESIS Search HIGH+LEVEL+SYNTHESIS
2 BEHAVIORAL SYNTHESIS 11 35% 3% 26 Search BEHAVIORAL+SYNTHESIS Search BEHAVIORAL+SYNTHESIS
3 MODULE SELECTION 9 59% 1% 10 Search MODULE+SELECTION Search MODULE+SELECTION
4 MULTIPLE VOLTAGES 5 63% 1% 5 Search MULTIPLE+VOLTAGES Search MULTIPLE+VOLTAGES
5 MULTIPLE VOLTAGE SCHEDULING 4 75% 0% 3 Search MULTIPLE+VOLTAGE+SCHEDULING Search MULTIPLE+VOLTAGE+SCHEDULING
6 HIGH LEVEL SYNTHESIS HLS 4 35% 1% 9 Search HIGH+LEVEL+SYNTHESIS+HLS Search HIGH+LEVEL+SYNTHESIS+HLS
7 DATA PATH SYNTHESIS 4 41% 1% 7 Search DATA+PATH+SYNTHESIS Search DATA+PATH+SYNTHESIS
8 FAULT SECURITY 3 57% 0% 4 Search FAULT+SECURITY Search FAULT+SECURITY
9 CONTROL FLOW INTENSIVE BEHAVIORS 3 100% 0% 3 Search CONTROL+FLOW+INTENSIVE+BEHAVIORS Search CONTROL+FLOW+INTENSIVE+BEHAVIORS
10 DYNAMIC FREQUENCY CLOCKING 3 100% 0% 3 Search DYNAMIC+FREQUENCY+CLOCKING Search DYNAMIC+FREQUENCY+CLOCKING

Key Words Plus


Rank Web of Science journal category Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class
1 HIGH LEVEL SYNTHESIS 24 34% 7% 58
2 ARCHITECTURAL SYNTHESIS 17 100% 1% 8
3 BEHAVIORAL SYNTHESIS 8 35% 2% 18
4 DIGITAL SYSTEMS 6 30% 2% 18
5 DATA PATH SYNTHESIS 6 71% 1% 5
6 MULTIPLE VOLTAGES 4 50% 1% 6
7 CODE MOTIONS 3 100% 0% 3
8 LEVEL EXPLORATION 2 67% 0% 2
9 STOCHASTIC EVOLUTION 2 67% 0% 2
10 DATA PATHS 2 50% 0% 3

Journals

Reviews


Title Publ. year Cit. Active
references		 % act. ref.
to same field
DATA-PATH SYNTHESIS 1994 20 5 100%
HIGH-LEVEL SYNTHESIS - CURRENT STATUS AND FUTURE-PROSPECTS 1995 0 20 95%
Designing electronic engines with electronic engines: 40 years of bootstrapping of a technology upon itself 2000 2 19 21%

Address terms


Rank Address term Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ.
in class
1 SYST IP CORE 2 67% 0.2% 2
2 DESIGN METHODOL 1 100% 0.2% 2
3 ELE A 1 50% 0.1% 1
4 KANAK KU 1 50% 0.1% 1
5 SYST IC BUSINESS 1 50% 0.1% 1
6 SYST PERCEPT 1 50% 0.1% 1
7 WIRELESS INFRASTRUCT BRANCH 1 50% 0.1% 1
8 DIGITAL DESIGN ENVIRONM 1 29% 0.2% 2
9 DPTO ARQUITECTURA COMP AUTOMAT 1 20% 0.4% 3
10 COMP ARCHITECTURE SYST ENGN 1 19% 0.4% 3

Related classes at same level (level 1)


Rank Relatedness score Related classes
1 0.0000256159 HARDWARE SOFTWARE PARTITIONING//HARDWARE SOFTWARE COSYNTHESIS//PROCESSOR SYNTHESIS
2 0.0000174948 POWER ESTIMATION//SWITCHING ACTIVITY//BUS ENCODING
3 0.0000163704 STREAMIT//SYNCHRONOUS DATAFLOW//DESIGN AUTOMATION FOR EMBEDDED SYSTEMS
4 0.0000138861 STATE ASSIGNMENT//FSM SYNTHESIS//LOGIC SYNTHESIS
5 0.0000125860 REGISTER ALLOCATION//INSTRUCTION SCHEDULING//INSTRUCTION LEVEL PARALLELISM
6 0.0000115127 CLOCK TREE//CLOCK SKEW//CLOCK DISTRIBUTION
7 0.0000107745 RECONFIGURABLE COMPUTING//INSTRUCTION SET EXTENSION ISE//ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS
8 0.0000100809 BITWIDTH//WORD LENGTH OPTIMIZATION//BIT WIDTH ALLOCATION
9 0.0000082884 CODE TRANSFORMATIONS//DUAL RING USAGE//SIMPLIFIED PROTOCOL
10 0.0000081912 ADDER CIRCUITS//CIRCUIT DESIGN FAULT TOLERANCE//UNDEFINEDNESS