Class information for:
Level 1: CHANNEL ROUTING//OVER THE CELL ROUTING//VLSI LAYOUT

Basic class information
ID Publications Average number
of references		 Avg. shr. active
ref. in WoS
11884 882 16.5 28%


Bar chart of Publication_year

Last years might be incomplete

Classes in level above (level 2)


ID, lev.
above		 Publications Label for level above
2570 3228 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS//FLOORPLANNING//PHYSICAL DESIGN

Terms with highest relevance score


Rank Term Type of term Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class
1 CHANNEL ROUTING Author keyword 28 52% 4% 38
2 OVER THE CELL ROUTING Author keyword 12 86% 1% 6
3 VLSI LAYOUT Author keyword 11 31% 3% 29
4 CORNER STITCHING Author keyword 8 100% 1% 5
5 LAYER ASSIGNMENT Author keyword 7 38% 2% 15
6 SWITCHBOX ROUTING Author keyword 6 80% 0% 4
7 TRANSISTOR PLACEMENT Author keyword 6 100% 0% 4
8 VIA MINIMIZATION Author keyword 5 54% 1% 7
9 SINGLE ROW ROUTING Author keyword 5 55% 1% 6
10 ESCAPE ROUTING Author keyword 4 47% 1% 7

Web of Science journal categories

Author Key Words


Rank Web of Science journal category Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class		 LCSH search Wikipedia search
1 CHANNEL ROUTING 28 52% 4% 38 Search CHANNEL+ROUTING Search CHANNEL+ROUTING
2 OVER THE CELL ROUTING 12 86% 1% 6 Search OVER+THE+CELL+ROUTING Search OVER+THE+CELL+ROUTING
3 VLSI LAYOUT 11 31% 3% 29 Search VLSI+LAYOUT Search VLSI+LAYOUT
4 CORNER STITCHING 8 100% 1% 5 Search CORNER+STITCHING Search CORNER+STITCHING
5 LAYER ASSIGNMENT 7 38% 2% 15 Search LAYER+ASSIGNMENT Search LAYER+ASSIGNMENT
6 SWITCHBOX ROUTING 6 80% 0% 4 Search SWITCHBOX+ROUTING Search SWITCHBOX+ROUTING
7 TRANSISTOR PLACEMENT 6 100% 0% 4 Search TRANSISTOR+PLACEMENT Search TRANSISTOR+PLACEMENT
8 VIA MINIMIZATION 5 54% 1% 7 Search VIA+MINIMIZATION Search VIA+MINIMIZATION
9 SINGLE ROW ROUTING 5 55% 1% 6 Search SINGLE+ROW+ROUTING Search SINGLE+ROW+ROUTING
10 ESCAPE ROUTING 4 47% 1% 7 Search ESCAPE+ROUTING Search ESCAPE+ROUTING

Key Words Plus


Rank Web of Science journal category Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ. in
class
1 REGION QUERIES 8 100% 1% 5
2 BUILDING BLOCK LAYOUT 6 100% 0% 4
3 LIST QUAD TREES 6 100% 0% 4
4 MULTICOMMODITY FLOWS 5 26% 2% 16
5 PIN ASSIGNMENT 4 75% 0% 3
6 WIRABILITY 4 75% 0% 3
7 INTERCHANGEABLE TERMINALS 3 100% 0% 3
8 GATE MATRIX LAYOUT 2 44% 0% 4
9 FLIP CHIP DESIGN 2 50% 0% 3
10 CHANNEL ROUTER 1 100% 0% 2

Journals

Reviews


Title Publ. year Cit. Active
references		 % act. ref.
to same field
RECENT ADVANCES IN VLSI LAYOUT 1990 37 41 46%
CHANNEL ROUTING FOR INTEGRATED-CIRCUITS 1989 1 28 93%

Address terms


Rank Address term Relevance score
(tfidf)		 Class's shr.
of term's tot.
occurrences		 Shr. of publ.
in class containing
term		 Num. of
publ.
in class
1 IND POWER 2 67% 0.2% 2
2 BEIJING SOFTWARE 1 100% 0.2% 2
3 COMP CONTROL GRP 1 50% 0.1% 1
4 DESIGN TECHNOL SOL 1 50% 0.1% 1
5 SUPERCONDUCTING SYST 1 50% 0.1% 1
6 HBEREICH MATH MA 6 1 0 33% 0.1% 1
7 CORP SEMICOND DEV 0 18% 0.2% 2
8 PHYS DESIGN GRP 0 25% 0.1% 1
9 ELECT SYST INFORMAT ENGN 0 12% 0.2% 2
10 ADV LSI TECHNOL DEV 0 10% 0.1% 1

Related classes at same level (level 1)


Rank Relatedness score Related classes
1 0.0000180673 FLOORPLANNING//PHYSICAL DESIGN//PLACEMENT
2 0.0000109744 ETHERNET RING PROTECTION//RING LOADING PROBLEM//SONET RING
3 0.0000087312 DIRECT EXECUTION//IBM CELL BROADBAND ENGINE//LONGLEY RICE MODEL
4 0.0000059655 PATH COLORING//K SPLITTABLE FLOW//PARTITIONED OPTICAL PASSIVE STARS NETWORK
5 0.0000056757 STATE ASSIGNMENT//FSM SYNTHESIS//LOGIC SYNTHESIS
6 0.0000053579 STEINER RATIO//INVERSE FERMAT TORRICELLI PROBLEM//STEINER MINIMAL TREE
7 0.0000052526 ANALOG CIRCUIT SYNTHESIS//CIRCUIT SIZING//ANALOG DESIGN AUTOMATION
8 0.0000045462 AUTOGRAM BASED SPECIFICATION OF CONTROL UNITS//DESIGN OF RELIABLE CONTROL UNITS//FORMALIZED AND COMPUTER AIDED METHODS OF LOGIC DESIGN
9 0.0000043687 GRAPH DRAWING//CROSSING NUMBER//BOOK EMBEDDING
10 0.0000043407 ART GALLERY//ORTHOGONAL POLYGONS//ART GALLERY PROBLEMS